Multilayered Semiconductor Device with Penetration Electrodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in providing stable internal power supply to core chips without increasing current consumption or chip area, as existing methods either boost power consumption or enlarge the chip to compensate for voltage fluctuations.
Innovation Solution
The implementation of a multilayered semiconductor device structure where internal power supply generation circuits in multiple core chips are coupled via penetrating electrodes, allowing for shared electrical charges and reduced compensation capacitance, thereby stabilizing internal power supply voltages without increasing power consumption or chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If compensation capacitance is arranged in the semiconductor device to increase electrical charges for inhibiting voltage fluctuations, then voltage stability is improved, but chip area increases
Solution Approach 1:
Multiple internal power supply generation circuits in different core chips are merged by coupling their outputs together through penetration electrodes. This allows the circuits to share electrical charges and function collectively as a larger compensation capacitance, achieving voltage stability without requiring additional capacitance elements that would increase chip area.
Solution Approach 2:
The patent transitions from a planar arrangement of power supply circuits to a three-dimensional multilayered structure with penetration electrodes extending vertically through multiple core chips. This dimensional change enables electrical charge sharing across layers, effectively creating distributed compensation capacitance without increasing the planar chip area.
2Speed
If operating current of the power supply circuit is increased to improve response speed, then response speed is improved, but power consumption increases
Solution Approach 1:
The patent combines multiple internal power supply generation circuits from different core chips and couples their outputs together. This merging allows the circuits to share electrical charges, effectively creating a larger compensation capacitance that improves response speed without requiring any single circuit to operate at higher current levels, thus avoiding increased power consumption.
3Productivity
If multiple core chips are layered to increase integrated circuit scale while minimizing footprint, then circuit scale is improved, but internal power supply stability becomes challenging
Solution Approach 1:
The patent merges the internal power supply generation circuits from multiple layered core chips by coupling their outputs through penetration electrodes. This allows all core chips to share a common power supply network with distributed compensation capacitance, achieving voltage stability across the multilayered structure without requiring separate power supply circuits in each chip.
Solution Approach 2:
The penetration electrodes serve multiple functions: they provide electrical connections between external terminals and internal circuits, and simultaneously couple the outputs of internal power supply generation circuits from different core chips. This multi-functionality enables power supply stability across the multilayered device without adding dedicated stabilization structures.
Data Source
AI summary
A semiconductor device includes a first semiconductor chip located over a substrate; and a second semiconductor chip located over the first semiconductor chip, wherein the first semiconductor chip includes a first internal power supply generation circuit that generates a first internal power supply voltage supplied to a first internal circuit; a first penetration electrode formed from an upper surface of the first semiconductor chip to an underside of the first semiconductor chip and electrically connected to the first internal power supply generation circuit; a first reference voltage generation circuit that generates a first reference voltage; and a second penetration electrode formed from the upper surface of the first semiconductor chip to the underside of the first semiconductor chip and electrically connected to the first reference voltage generation circuit.