Multi-Layered Sidewall Spacers for Self-Aligned Contact Isolation
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Solution Overview
Problem
As semiconductor device dimensions decrease, the thickness of sidewall spacers becomes thinner, leading to potential short circuits between source/drain contacts and gate electrodes, necessitating improved electrical isolation in self-aligned contact structures.
Innovation Solution
The implementation of additional sidewall spacers and a contact etching stop layer to enhance electrical isolation between source/drain contacts and gate electrodes, achieved through a multi-layered spacer structure and precise etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are decreased to increase device density, then productivity is improved, but sidewall spacer thickness becomes thinner leading to potential short circuits between source/drain contacts and gate electrodes
Solution Approach 1:
The single sidewall spacer structure is segmented into multiple thinner spacer layers (first sidewall spacer layer, second sidewall spacer layer, third sidewall spacer layer) deposited sequentially. This segmentation allows each layer to be precisely controlled in thickness while collectively providing sufficient total thickness for electrical isolation, resolving the contradiction between reduced device dimensions and maintained isolation reliability.
Solution Approach 2:
The solution transitions from a single-dimensional spacer thickness parameter to a multi-layered vertical structure. By stacking multiple spacer layers with different materials (silicon oxide, silicon nitride, silicon oxynitride) in the vertical dimension, the patent achieves both thin overall profile (for high device density) and sufficient cumulative thickness (for electrical isolation reliability).
2Productivity
If sidewall spacer thickness is reduced to accommodate smaller device dimensions, then device density increases, but electrical isolation between source/drain contacts and gate electrodes deteriorates
Solution Approach 1:
Different regions of the sidewall spacer structure are assigned different material properties. The first sidewall spacer layer uses silicon oxide with specific dielectric properties, while the second and third layers use silicon nitride and silicon oxynitride with different electrical isolation characteristics. This local quality differentiation optimizes electrical isolation at each interface between source/drain contacts and gate electrodes while maintaining overall thin profile.
Solution Approach 2:
The sidewall spacer is constructed as a composite structure combining multiple dielectric materials (silicon oxide, silicon nitride, silicon oxynitride) in a stacked configuration. This composite approach leverages the complementary electrical isolation properties of different materials to achieve superior overall isolation performance that cannot be obtained with a single material, thereby maintaining reliability while enabling reduced device dimensions.
3Reliability
If additional sidewall spacers and contact etching stop layer are added to enhance electrical isolation, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple functions into the sidewall spacer structure: electrical isolation, dimensional definition for contact holes, and etching stop functionality. The contact etching stop layer is integrated into the spacer stack, serving both as part of the isolation structure and as the etching stop reference. This merging reduces the need for separate structures and processes, thereby limiting the increase in device complexity.
Solution Approach 2:
The multi-layered sidewall spacer structure serves multiple purposes simultaneously: providing electrical isolation between source/drain contacts and gate electrodes, defining the lateral dimensions for contact hole formation, and serving as the etching stop layer for contact hole etching. This multi-functionality justifies the increased structural complexity by eliminating the need for separate dedicated structures for each function.
Data Source
AI summary
A semiconductor device includes a gate structure disposed over a substrate, and sidewall spacers disposed on both side walls of the gate structure. The sidewall spacers includes at least four spacer layers including first to fourth spacer layers stacked in this order from the gate structure.