Multi-Layered Storage Node Fabrication for High Aspect Ratio Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for fabricating semiconductor devices with multi-layered storage nodes are costly and prone to poor opening of contact holes and poor filling of metal contacts due to high aspect ratios, leading to decreased capacitance and increased processing steps.
Innovation Solution
A semiconductor device and method that involves forming first and second storage nodes in a cell region and metal lines in a peripheral circuit region, using a barrier layer and dielectric structures to manage etching and prevent dipping out, with a protective layer to secure the metal lines and prevent damage during etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a high aspect ratio etching process is used to form open parts with increased height, then the capacitance of capacitors is improved, but the manufacturing complexity and difficulty of the etching process increases significantly
Solution Approach 1:
The patent divides the formation of storage nodes into multiple sequential stages using separate mold layers (first mold layer 141, second mold layer 142) and corresponding etching processes. This segmentation allows each etching step to work on manageable depth ranges, avoiding the need for a single high aspect ratio etching process while achieving the required total capacitance through stacked storage nodes (first storage nodes 41 and second storage nodes 42).
Solution Approach 2:
The patent transitions from forming storage nodes in a single vertical dimension to stacking storage nodes across multiple vertical layers. By introducing a second mold layer and forming second storage nodes above the first storage nodes, the capacitance accumulation moves from a single-depth etching challenge to a multi-layer stacking approach, effectively distributing the capacitance requirement across different vertical levels.
2Quantity of substance
If the height of the mold layer is increased to secure the capacitance of capacitors, then the capacitance is improved, but the aspect ratio of contact holes increases leading to poor opening and poor filling of metal contacts
Solution Approach 1:
The patent segments the mold structure into multiple layers (first mold layer 141, second mold layer 142) with corresponding segmented storage nodes. This segmentation prevents the formation of excessively deep contact holes by distributing the capacitance across multiple shallower layers, thereby maintaining acceptable aspect ratios for metal contact formation while achieving the required total capacitance.
Solution Approach 2:
The patent introduces a second mold layer 142 as an intermediary structure that enables the formation of second storage nodes 42 above the first storage nodes 41. This intermediary layer acts as a platform that distributes the capacitance accumulation across two separate mold layers, preventing any single contact hole from becoming too deep and maintaining manufacturing precision for metal contact filling.
3Quantity of substance
If storage nodes are formed into double layers using separate mold layers and etching processes, then the capacitance is improved, but the number of processing steps increases markedly
Solution Approach 1:
The patent merges the formation processes of first and second storage nodes by using a unified barrier layer 161 and unified conductive layer 121 for both layers. The barrier layer 161 is formed once to cover the entire surface, and the conductive layer 121 is deposited once to form both first storage nodes 41 and second storage nodes 42 simultaneously after selective etching, reducing the number of separate barrier layer formation and conductive layer deposition steps.
Solution Approach 2:
The barrier layer 161 serves multiple functions: it acts as a barrier for both first and second storage nodes, provides a common base for forming both layers of storage nodes, and enables unified processing for both layers. The conductive layer 121 also serves dual purposes by forming both first storage nodes and second storage nodes in a single deposition step, reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, secures capacitance, reduces processing steps by 10-15%, and prevents poor opening of contact holes and incomplete filling of metal contacts, thereby enhancing the reliability of the semiconductor device.
Implementation Method 1
an etching process for forming the open parts is to be used in a DRAM fabrication process. The open parts are obtained by etching a mold layer
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a first dielectric structure over a second region of a substrate to expose a first region of the substrate, forming a barrier layer over an entire surface including the first dielectric structure, forming a second dielectric structure over the barrier layer in the first region, forming first open parts and second open parts in the first region and the second region, respectively, by etching the second dielectric structure, the barrier layer and the first dielectric structure, forming first conductive patterns filled in the first open parts and second conductive patterns filled in the second open parts, forming a protective layer to cover the second region, and removing the second dielectric structure.