Multilevel Addressing Scheme for Non-Volatile Memory Wear Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Previous storage systems face challenges in writing vital information to a location at a single address level, as the number of power downs exceeds the memory cells' write limit, leading to premature wear and reduced lifespan.
Innovation Solution
Implementing a multilevel addressing scheme that performs multiple reads to determine the starting address of vital information, using intermediate addresses that change periodically to distribute the write load across multiple address levels, thereby extending the lifespan of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single address level is used to store vital information, then the initialization process is simple and direct, but the memory cells at that location are written excessively during power downs, exceeding their write limit and reducing lifespan
Solution Approach 1:
The patent transitions from a single address level to multiple address levels (e.g., first address level, second address level, third address level) to store vital information. This dimensional expansion allows the system to distribute write operations across multiple locations, preventing any single memory cell from being overwritten excessively during power downs, thus resolving the contradiction between operational simplicity and memory cell lifespan.
Solution Approach 2:
The patent segments the storage of vital information across multiple address levels rather than concentrating it at a single location. By dividing the information storage function across several address levels, the system reduces the write frequency at each individual location, thereby extending memory cell lifespan while maintaining the ability to retrieve vital information during initialization.
2Reliability
If vital information is written to the same location during each power down, then the information is consistently updated, but the write count at that location exceeds the memory cells' write limit
Solution Approach 1:
The patent merges multiple address levels to store different portions or aspects of vital information. By combining the storage function across multiple locations (first address level, second address level, third address level), the system maintains reliable information updates while distributing the write load, preventing premature wear at any single location.
Solution Approach 2:
The patent introduces intermediate address levels as mediators between the initialization process and the final storage location. These intermediate levels allow the system to update vital information consistently across power downs while redirecting write operations away from any single memory cell, thereby reducing harmful wear effects.
3Duration of action of stationary object
If multiple reads are performed to determine the starting address using multilevel addressing, then the write load is distributed across multiple address levels extending memory lifespan, but the initialization process becomes more complex
Solution Approach 1:
The patent uses multiple address levels (adding a dimensional layer to address storage) to distribute write operations and extend memory lifespan. Although this requires multiple reads during initialization, the structured hierarchical approach organizes the complexity in a manageable way, trading moderate initialization complexity for significant gains in memory cell lifespan.
Solution Approach 2:
The patent performs preliminary actions by establishing the multilevel addressing structure and determining the starting address through multiple reads during initialization. This preliminary setup, while more complex than single-level addressing, is performed once and enables the system to distribute subsequent write operations effectively, extending memory lifespan for the remainder of the device's operation.
Data Source
AI summary
In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.