Multilevel Bitline Layout for Lower 3D NAND Capacitance
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Solution Overview
Problem
The increasing capacitance between adjacent bitlines in electronic devices, such as 3D NAND devices, due to reduced dimensions and spacing, hinders further reduction in pitch, affecting programming and reading times.
Innovation Solution
Implementing multilevel bitlines with dielectric materials and air gaps to separate bitlines at different levels, reducing capacitance and enabling smaller pitches without physical contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch of bitlines is decreased to increase integration density, then the level of integration improves, but the capacitance between adjacent bitlines increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of bitlines to a three-dimensional stacked configuration. Bitlines are arranged in multiple vertical levels (first level and second level) with dielectric materials and air gaps providing separation. This vertical stacking enables higher integration density while maintaining acceptable capacitance levels through increased spatial separation in the vertical dimension.
Solution Approach 2:
Dielectric materials and air gaps are introduced as intermediary substances between adjacent bitlines at different levels. These intermediaries provide electrical isolation and reduce capacitive coupling between bitlines, enabling closer spacing and higher density without proportionally increasing capacitance.
2Productivity
If the dimensions of memory cells are reduced to increase density, then the integration level improves, but the programming and reading time increases
Solution Approach 1:
By stacking bitlines in multiple vertical levels with proper spacing, the patent achieves higher integration density without requiring further reduction in lateral dimensions. This maintains acceptable bitline lengths and widths, thereby keeping resistance and capacitance values manageable and programming/reading times acceptable.
Solution Approach 2:
The dielectric materials and air gaps between bitline levels reduce capacitive coupling, which helps maintain faster signal transitions and reduces the time required for programming and reading operations despite increased integration density.
3Productivity
If the pitch of bitlines is decreased to increase density, then the integration density improves, but the bitline-bitline capacitance increases
Solution Approach 1:
The patent utilizes vertical stacking to achieve density improvements without proportionally decreasing lateral pitch. Bitlines at different vertical levels can be spaced farther apart in three-dimensional space than would be possible in a purely two-dimensional layout, reducing capacitance while maintaining density.
Solution Approach 2:
Dielectric materials and air gaps serve as intermediary layers between bitline levels, providing electrical isolation that reduces capacitive coupling. This enables tighter lateral spacing for higher density while the vertical intermediaries mitigate the capacitance increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves lower bitline-bitline capacitance and resistance, allowing for further scaling and improved performance in electronic devices.
Implementation Method 1
capacitance between adjacent bitlines increases
Implementation Method 2
separated from one another by a dielectric material or by an air gap
Data Source
AI summary
An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.