Multilevel Bitline Layout for Lower Capacitance in 3D NAND
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Solution Overview
Problem
As electronic devices, such as 3D NAND devices, are scaled down to increase integration density, the capacitance between adjacent bitlines increases, leading to longer programming and read times. This limits the further reduction of bitline pitch due to the smaller dimensions and closer spacing of memory cells.
Innovation Solution
The implementation of multilevel bitlines, where bitlines are positioned at multiple levels with dielectric materials or air gaps used to separate them, reduces bitline-bitline capacitance. This configuration includes L1 bitlines proximal to the base material and L2 bitlines distal to the base material, with a liner separating them from each other and from the L2 contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch of bitlines is decreased to increase integration density, then the integration density is improved, but the bitline-bitline capacitance increases
Solution Approach 1:
The patent transitions from a planar (2D) bitline arrangement to a three-dimensional (3D) multilevel structure. Bitlines are positioned at multiple vertical levels (e.g., first level and second level) with lateral offsets, allowing increased integration density while maintaining adequate spacing between adjacent bitlines at the same level. This dimensional change enables continued scaling without the capacitance penalty of reduced pitch.
Solution Approach 2:
The bitline system is segmented into multiple independent levels (first level bitlines and second level bitlines). Each level contains a subset of the total bitlines, and the levels are spatially separated by dielectric materials and air gaps. This segmentation reduces the number of bitlines at any given horizontal plane, thereby reducing capacitive coupling while maintaining high overall integration through vertical stacking.
2Quantity of substance
If the dimensions of memory cells are reduced to increase integration density, then the integration density is improved, but the bitline-bitline capacitance increases
Solution Approach 1:
By introducing vertical separation between bitlines at different levels, the patent decouples the relationship between memory cell size and bitline spacing. Smaller memory cells can be packed more densely without necessarily reducing the horizontal pitch of bitlines, since bitlines are distributed across multiple vertical levels. The lateral offset between levels ensures adequate spacing is maintained even as memory cell dimensions shrink.
3Object-affected harmful factors
If multilevel bitlines are implemented to reduce bitline-bitline capacitance, then the bitline-bitline capacitance is reduced, but the device complexity increases
Solution Approach 1:
The patent combines multiple bitline levels into a unified memory array architecture where first level bitlines and second level bitlines operate together. The bitlines at different levels are laterally offset and connected to the same or different memory cell arrays, creating an integrated multilevel structure that achieves capacitance reduction while maintaining architectural coherence and simplifying control compared to fully independent bitline systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multilevel bitline configuration effectively reduces bitline-bitline capacitance, allowing for smaller pitches while maintaining or improving electrical performance, thus enabling further scaling of electronic devices without compromising read and write times.
Implementation Method 1
capacitance between adjacent bitlines increases
Implementation Method 2
separated from the first bitlines and from the second bitlines by dielectric materials and air gaps
Data Source
AI summary
An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.