Multi-Level Bus Encoding with DBI for Lower-Power Memory Signaling
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Solution Overview
Problem
In modern memory systems, increasing clock speeds lead to higher power consumption in multi-level signaling due to disparities in performance between memory and logic transistors, making it difficult to scale bandwidth effectively.
Innovation Solution
The implementation of an apparatus comprising an encoding circuit, multi-level encoder, multi-level decoder, and decoding circuit that employs data bus inversion (DBI) encoding algorithms to encode data, reducing power consumption by minimizing transitions in data signals, and using multi-level drivers to provide multi-level signals corresponding to various voltage levels representing multiple bits of data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-level signaling is used to increase bandwidth, then data throughput increases, but power consumption increases
Solution Approach 1:
The patent applies parameter changes by modifying the voltage levels of signal transitions. Instead of using full-swing voltage transitions for all data bits, the system uses reduced voltage swing for certain transitions and combines multiple data bits into single multi-level voltage transitions. This changes the electrical parameters of signal transmission to reduce dynamic power consumption while maintaining data throughput through efficient encoding schemes like 64b/66b encoding and transition optimization.
2Productivity
If clock speed is increased to maintain bandwidth, then data transfer rate increases, but power consumption increases
Solution Approach 1:
The patent employs periodic action through optimized clocking schemes where clock signals are activated only when necessary for data transitions. The system uses transition-detect clocking where the clock enables data latches only during valid transition periods, rather than continuously clocking all data paths. This periodic activation of clocking reduces dynamic power consumption associated with continuous clock distribution and latch switching while maintaining effective bandwidth through efficient use of clock cycles.
3Productivity
If multi-level drivers are used to provide multi-level signals, then bandwidth efficiency improves, but power consumption varies with data patterns
Solution Approach 1:
The patent applies preliminary action through pre-computation of transition patterns and encoding optimization. The encoding circuit performs 64b/64b or 64b/66b encoding in advance, identifying opportunities for transition cancellation and combining multiple data transitions into single multi-level voltage transitions before the actual data transmission occurs. This preliminary processing optimizes the data pattern to minimize the number and magnitude of voltage transitions, thereby reducing power consumption while maintaining bandwidth efficiency through the pre-optimized encoding scheme.
Data Source
AI summary
Methods and apparatuses for providing multi-level encoded signals are disclosed. An apparatus may include an encoding circuit and a multi-level encoder. The encoding circuit may be configured to receive data and provide encoded data based, at least in part on the data. The multi-level encoder may be coupled to the encoding circuit and configured to receive the encoded data. The multi-level encoder may be further configured to provide the encoded data to a bus as multi-level signal responsive, at least in part, to receipt of the encoded data.