Adaptive Multibit Bus Using Voltage Levels for GPU Interconnects

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Solution Overview

Problem

Complex GPUs face wire congestion due to the use of single-bit transmission wires, leading to delays and increased power consumption, which limits device usage and efficiency.

Innovation Solution

An adaptive multibit bus is introduced, allowing two bits of data to be transmitted over a single-bit wire by utilizing intermediate voltage levels, enabling higher system frequency without area sacrifices and reducing design value, and dynamically switching between data transmission modes based on voltage levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If single-bit transmission wires are used in complex GPUs, then device area is reduced, but wire congestion increases leading to delays and increased power consumption

Engineering Contradiction:
Improvedevice areaVSAvoidprocessing speed
Core Design Contradiction:
Area of stationary objectVSProductivity

Solution Approach 1:

The patent merges multiple data transmission channels into a single wire by encoding two bits of data onto one physical wire using voltage level modulation. This combining approach reduces the number of physical wires needed, decreasing wire congestion and associated power consumption while maintaining data transmission capacity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the voltage level parameter of the transmission wire to encode multiple bits of data. By utilizing different voltage levels (e.g., high, medium, low) on a single wire, the system can represent multiple data states, effectively increasing the information capacity of the wire without adding physical wires.

Inventive Principle:
Principle #35Parameter changes

2Area of stationary object

If single-bit transmission wires are used in complex GPUs, then device area is reduced, but power consumption increases

Engineering Contradiction:
Improvedevice areaVSAvoidpower consumption
Core Design Contradiction:
Area of stationary objectVSLoss of energy

Solution Approach 1:

The patent merges multiple data transmission channels into a single wire by encoding two bits of data onto one physical wire using voltage level modulation. This combining approach reduces the number of physical wires needed, decreasing wire congestion and associated power consumption while maintaining data transmission capacity.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If voltage levels are increased to transmit more data, then data transmission capacity increases, but power consumption increases

Engineering Contradiction:
Improvedata transmission capacityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent changes the voltage level parameter of the transmission wire to encode multiple bits of data. By utilizing different voltage levels (e.g., high, medium, low) on a single wire, the system can represent multiple data states, effectively increasing the information capacity of the wire without adding physical wires.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances system performance by increasing frequency at higher voltage levels while reducing power consumption and maintaining efficiency, allowing GPUs to enter low power states sooner.

Implementation Method 1

transmitting two bits of data on the single-bit interconnect... utilizing intermediate voltage levels

Methodology Applied
Scientific EffectVoltage level encoding:

Data Source

PatentUS10490170B2Adaptive multibit bus for energy optimization
Publication Date: 2019.11.26 INTEL CORP
  • US10490170B2 patent drawing
  • US10490170B2 patent drawing
  • US10490170B2 patent drawing

AI summary

Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.