Multilevel Carrier for Compound Semiconductor Device Parasitic Inductance Reduction
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Solution Overview
Problem
Semiconductor devices experience undesired parasitic effects such as inductance during operation due to the electrical coupling of semiconductor chips, which can negatively impact switching performance and device efficiency.
Innovation Solution
The use of a multilevel carrier structure with compound semiconductor chips and control semiconductor chips arranged on different levels, where the electrical connection between them is minimized to reduce parasitic inductance, resulting in a compact design and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor chips are electrically coupled in separated packages, then communication between chips is established, but parasitic inductance increases
Solution Approach 1:
The patent transitions from a planar arrangement of semiconductor chips to a three-dimensional stacked configuration using a multilevel carrier. Chips are arranged on different levels (first level, second level, third level) vertically stacked, with electrical connections made through vertical vias and conductive paths. This dimensional change reduces the horizontal distance between chips, thereby minimizing parasitic inductance while maintaining reliable communication.
Solution Approach 2:
The patent combines multiple semiconductor chips and their interconnection structures into a single integrated package with a multilevel carrier. The carrier merges the support structure, electrical interconnections, and chip mounting platforms into one unified component, reducing the overall package size and minimizing the length of electrical pathways between chips, thus reducing parasitic inductance.
2Object-generated harmful factors
If electrical coupling length is reduced, then parasitic inductance decreases, but device complexity increases
Solution Approach 1:
The multilevel carrier is segmented into distinct functional levels: a first level for mounting power semiconductor chips, a second level for control semiconductor chips, and a third level for additional components. Each level has dedicated mounting areas, vias, and conductive paths optimized for specific functions. This segmentation allows for modular assembly and simplifies the manufacturing process despite the three-dimensional complexity.
Solution Approach 2:
The patent implements a nested structure where smaller components are placed within or between larger structural elements. Control chips are positioned on the second level between the power chips on the first level and additional components on the third level. The electrical interconnections are nested within vertical vias that pass through the carrier structure, efficiently utilizing the three-dimensional space while minimizing external connection lengths.
Data Source
AI summary
A device includes a carrier having a first carrier section on a first level and a second carrier section on a second level different from the first level. The device further includes a compound semiconductor chip arranged over the first carrier section and a control semiconductor chip arranged over the second carrier section. The control semiconductor chip is configured to control the compound semiconductor chip. An encapsulation material covers the compound semiconductor chip and the control semiconductor chip.