Multi-Level CDR Circuit With Fewer Comparators for Phase Detection
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Solution Overview
Problem
In reception circuits for multi-level signals, the increased number of comparing circuits required to detect phase differences leads to higher power consumption, while reducing the number of threshold values compromises detection rate and tracking performance.
Innovation Solution
A clock data recovery (CDR) circuit with a data determining circuit using three threshold values to determine data signal values and a phase detecting circuit that detects data patterns in consecutive symbols, generating a phase difference signal to adjust the clock signal's phase, thereby reducing the number of comparing circuits while maintaining detection rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of comparing circuits is increased to detect phase differences in multi-level signals, then the detection rate and tracking performance are improved, but the power consumption increases
Solution Approach 1:
The patent extracts only the essential comparison operations needed for phase detection by identifying and utilizing specific data patterns (monotonic increasing/decreasing patterns) rather than comparing all possible data combinations. This selective approach reduces the number of comparing circuits while maintaining adequate detection capability.
Solution Approach 2:
The phase detecting circuit is designed to perform multiple functions: it detects phase differences, identifies data patterns, and controls clock signal phases using a unified structure. The same circuit infrastructure serves both data determination and phase detection purposes, reducing the need for separate dedicated comparing circuits.
2Use of energy by moving object
If the number of comparing circuits is reduced to decrease power consumption, then the detection rate and tracking performance deteriorate
Solution Approach 1:
The patent changes the detection parameter from comparing all possible data combinations to specifically detecting monotonic increasing/decreasing patterns. This parameter change allows the system to maintain detection effectiveness with fewer comparing circuits by focusing on the most informative data patterns for phase detection.
Solution Approach 2:
The system performs preliminary identification of data patterns (monotonic increasing/decreasing) before executing phase detection comparisons. This preliminary action filters the data stream to only those patterns that provide useful phase information, reducing the burden on comparing circuits while maintaining detection rate.
3Measurement precision
If traditional MM-type or BB-type phase detecting circuits are used, then phase difference detection is achieved, but the number of comparing circuits increases leading to higher power consumption
Solution Approach 1:
The patent extracts only the necessary comparison operations by identifying specific monotonic data patterns rather than implementing full MM-type or BB-type comparison logic. This extraction reduces the circuit complexity while preserving the essential phase detection capability.
Solution Approach 2:
Instead of using traditional approaches that start with comprehensive comparison circuits and try to optimize them, the patent inverts the approach by starting with the desired outcome (phase detection) and working backward to identify only the minimal set of comparison operations needed, achieving simpler circuit design.
Data Source
AI summary
A CDR circuit includes a data-determination-circuit to determine a value of a data-signal, based on a first comparison-result of comparing the data-signal with first threshold-values at a timing of a clock-signal, a comparison-circuit to compare the data-signal with a second threshold-value at the timing to generate a second comparison-result, a phase-detection-circuit to detect data-patterns in which first to third symbols are temporally consecutive, based on a determination-result, the data-patterns forming that a value of the second symbol is larger than the first symbol and smaller than the third symbol, or the in value of the second symbol is smaller than the first symbol and larger than the third symbol, wherein the phase-detection-circuit generates a phase-difference-signal for controlling a phase of the clock-signal to advance or delay, based on the second comparison-result at the second symbol, and a phase-adjustment-circuit to adjust the phase of the clock-signal based on the phase-difference-signal.