Multilevel-Cell Memory Structures Using Tungsten Oxide Regions
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Solution Overview
Problem
Existing high-density memory technologies face challenges in manufacturing cost and simplicity, particularly in stacking multiple planar arrays of memory devices, which require efficient and reliable methods to achieve high data density.
Innovation Solution
The development of multilevel-cell memory structures using tungsten oxide regions that provide different read current levels for multiple logic states, allowing each memory layer structure to store two bits of information, thereby increasing storage capacity to 16 logic states by using a tungsten oxide region extending into a tungsten plug member surrounded by a barrier member, with critical dimensions optimized for manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple planar arrays of memory devices are stacked to increase data density, then storage capacity is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent transitions from two-dimensional planar arrays to three-dimensional stacked memory structures by vertically stacking multiple memory layers (first memory layer structure and second memory layer structure) with each layer containing memory cells formed at crosspoints of word lines and bit lines, thereby increasing storage capacity without proportionally increasing manufacturing complexity
Solution Approach 2:
The memory device is divided into multiple independent memory layer structures that can be manufactured and stacked separately, with each layer containing segmented functional components (word lines, bit lines, memory cells with p+ polysilicon anodes and n- polysilicon cathodes) that simplify the overall manufacturing process while achieving high density
2Quantity of substance
If tungsten oxide regions are used to define multiple read current levels for multilevel-cell function, then storage capacity per layer is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses tungsten oxide regions with varying critical dimensions to define different read current levels, where the resistance of the tungsten oxide varies with its dimensional parameters, enabling multilevel-cell functionality that stores multiple bits per memory location through programmable resistance states
Solution Approach 2:
Different regions of the memory structure have locally optimized properties, with tungsten oxide regions specifically engineered with particular critical dimensions to provide desired resistance characteristics for different logic states, while other regions maintain standard dimensions, allowing tailored performance without uniform precision requirements across the entire device
3Reliability
If barrier members surround tungsten plug members to improve reliability, then device reliability is improved, but manufacturing steps increase
Solution Approach 1:
The barrier members surrounding the tungsten plug members are formed through self-aligned processes where the barrier material is deposited conformally on the tungsten structure, automatically providing the required dimensional alignment and protection without additional alignment steps, thereby improving reliability while maintaining manufacturing simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density memory devices with improved manufacturing simplicity and reliability, allowing for efficient storage of multiple bits per memory layer structure, enhancing data density without increasing manufacturing complexity.
Implementation Method 1
a tungsten oxide region that provides different read current levels for a plurality of logic states
Data Source
AI summary
The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.