Multi-Level Chip Enable Circuit for Stacked Memory Selection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current storage devices with multi-stack memory configurations face limitations in chip size reduction and integration due to the need for separate chip enable signals and address allocation for each memory chip, which hinders efficiency and increases the time required for command and address transmission.
Innovation Solution
A storage device that generates a multi-level chip enable signal using a daisy-chain structure of resistors connected between pins and a voltage terminal, allowing multiple memory chips to share a common signal and eliminating the need for individual chip address allocation by generating reference voltage periods that correspond to specific voltage levels, thereby selecting the appropriate memory chip based on the signal level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate chip enable signals and address allocation are used for each memory chip, then each chip can be independently controlled, but chip size reduction and integration are limited
Solution Approach 1:
The patent combines multiple chip enable signals into a single multi-level chip enable signal that can simultaneously control multiple memory chips. By encoding chip selection information in voltage levels rather than using separate signals, the system achieves independent chip control while reducing signal complexity and improving integration.
Solution Approach 2:
The patent changes the parameter of the chip enable signal from binary (high/low) to multi-level (multiple voltage levels), where each voltage level corresponds to a specific memory chip. This parameter change eliminates the need for separate address allocation and enables efficient chip selection in multi-stack configurations.
2Measurement precision
If individual chip addresses are allocated for each memory chip, then chip identification is accurate, but the time required for command and address transmission increases
Solution Approach 1:
The patent performs preliminary encoding of chip identification information into voltage levels during the chip enable signal generation. This preliminary action eliminates the need for subsequent address transmission and comparison steps, thereby reducing transmission time while maintaining accurate chip identification through voltage level detection.
Solution Approach 2:
The patent extracts the chip address information from the traditional address bus and embeds it directly into the chip enable signal's voltage levels. This extraction eliminates the need for separate address transmission, reducing the time required for command and address delivery while preserving accurate chip identification.
3Quantity of substance
If multiple memory chips are stacked to increase capacity, then storage density improves, but chip enable signal management becomes more complex
Solution Approach 1:
The patent creates a universal chip enable signal that can address multiple memory chips in a multi-stack configuration. By using voltage levels to encode chip identifiers, a single signal line performs the function of multiple separate control lines, simplifying signal management while supporting increased storage capacity through vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the size of memory chips, improves integration, and enhances the efficiency of input/output interfaces by eliminating the need for separate chip addresses and reducing the time required for chip selection, leading to improved performance and reduced complexity in multi-stack memory configurations.
Implementation Method 1
The plurality of memory chips are configured to respectively generate a plurality of reference voltage periods that divide between a voltage level of the third pin and a voltage level of the first voltage terminal based on plurality of resistors
Data Source
AI summary
A storage device includes a controller including first and second pins and configured to output a multi-level chip enable signal through the second pin, and a memory device. The memory device includes third and fourth pins respectively connected to the first and second pins, and a plurality of memory chips commonly connected to the fourth pin. The plurality of memory chips respectively include a plurality of resistors connected to one another in a daisy-chain structure between the third pin and a first voltage terminal. The plurality of memory chips are configured to respectively generate a plurality of reference voltage periods that divide between a voltage level of the third pin and a voltage level of the first voltage terminal based on the plurality of resistors.