Multi-Level Delay Clocking for Register-Efficient Signal Delay
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Solution Overview
Problem
Existing signal delaying methods require a large number of registers to handle larger data volumes, leading to increased storage occupancy and inefficiency in signal delaying circuits.
Innovation Solution
A method and system that determine the total quantity of delay phases for a drive signal by using multiple levels of delay clock signals with decreasing clock periods, allowing for sequential delay of the signal across these levels, reducing the need for registers and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional signal delaying methods are used, then signal delaying can be achieved, but a large number of registers are required leading to increased storage occupancy and reduced efficiency
Solution Approach 1:
The patent divides the signal delaying function into multiple segments by using different numbers of registers for different data volumes. Specifically, it uses a first number of registers for first data volume and a second number of registers for second data volume, where the second number is less than the first. This segmentation allows the system to optimize register usage based on actual needs, reducing overall storage occupancy while maintaining delaying effectiveness.
Solution Approach 2:
The patent changes the parameter of register quantity based on data volume characteristics. By dynamically adjusting the number of registers used according to the data volume being processed, the system achieves efficient signal delaying with minimized storage resources. This parameter change strategy allows flexible adaptation to different operating conditions.
2Adaptability or versatility
If more registers are used to handle larger data volumes, then signal delaying capacity increases, but storage occupancy and circuit complexity increase
Solution Approach 1:
The patent implements a dynamic register allocation strategy where the number of registers is not fixed but adapts based on data volume requirements. The system can switch between different register configurations (first number for first data volume, second number for second data volume), making the circuit structure dynamic rather than static. This dynamic approach allows the system to handle varying data volumes efficiently without permanently committing to a complex high-capacity configuration.
Solution Approach 2:
The patent applies different register allocation strategies to different data volume scenarios. Instead of using a uniform high-capacity register configuration for all cases, it tailors the register quantity to the specific data volume being processed. This local quality approach ensures that each part of the system operates with optimally sized resources, reducing overall circuit complexity while maintaining adequate handling capacity.
Data Source
AI summary
Provided is a method for delaying signals. The method includes: determining a total quantity of delay phases by which a drive signal is to be delayed; determining, based on a clock period of each level of delay clock signals of a plurality of levels of delay clock signals, a quantity of clock periods of each level of delay clock signals that are required for delaying by the total quantity of delay phases, wherein the clock periods of the levels of delay clock signals decrease sequentially from a first level to a last level; and delaying the drive signal by the quantities of clock periods of the levels of delay clock signals sequentially in descending order, and outputting the drive signal after delay.