Multi-Level Contact Formation in Integrated Circuit Stacks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The fabrication of integrated circuits with multi-level metal stacks requires a large number of expensive masking steps, making the process costly and time-consuming.
Innovation Solution
A method for forming a multi-level stack with a multi-level contact that involves forming a specified number of conductive layers and insulating layers, followed by etching vias in a via formation layer at the edge of the stack to create self-aligned multi-level contacts, reducing the need for multiple masking steps and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional multi-level metal stacks are fabricated using sequential masking steps for each metal line, then each metal line can be formed with proper contacts, but the number of masking steps increases significantly, making the process expensive and time-consuming
Solution Approach 1:
The patent divides the contact formation process into two distinct stages: (1) forming all conductive layers and insulating layers without forming contacts between them, and (2) subsequently forming vias and multi-level contacts that penetrate through multiple insulating layers to connect conductive layers. This segmentation eliminates the need for sequential masking steps for each contact, reducing the total number of masking operations while maintaining alignment precision through the via formation approach.
Solution Approach 2:
The patent transitions from planar contact formation to vertical via-based contact formation. Instead of forming contacts in the lateral dimension through sequential masking and etching, the invention forms vias that extend vertically through multiple insulating layers, allowing multi-level contacts to be established in a single via formation step rather than multiple sequential steps.
2Productivity
If the number of masking steps is reduced to improve productivity, then fabrication cost and time decrease, but maintaining precise alignment and critical dimensions becomes more difficult
Solution Approach 1:
The patent performs preliminary actions by forming all conductive layers and insulating layers in advance before forming any contacts. The via formation layer is deposited and patterned to define via locations that will subsequently define contact positions. This preliminary via patterning establishes a reference framework that guides subsequent contact formation, ensuring precise alignment and critical dimension control even with reduced masking steps.
Solution Approach 2:
The via formation layer serves as an intermediary element between the insulating layers and the final contacts. By forming vias through this intermediate layer first, the patent creates a structured pathway that maintains precise geometric control. The via dimensions and positions are established before contact material deposition, ensuring that critical dimensions are controlled through the via formation process rather than through multiple contact-specific masking steps.
Data Source
AI summary
A method for forming a multi-level stack having a multi-level contact is provided. The method includes forming a multi-level stack comprising a specified number, n, of conductive layers and at least n−1 insulating layers. A via formation layer is formed over the stack. A first via is etched in the via formation layer at a first edge of the stack. A first multi-level contact is formed in the first via. For a particular embodiment, a second via may be etched in the via formation layer at a second edge of the stack and a second multi-level contact may be formed in the second via.