H-Type Multilevel Converter Bus Layout for Inductance Cancellation
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Solution Overview
Problem
High-voltage and high-power multilevel inverters in electrified powertrain systems face issues with capacitor voltage imbalance and overvoltage stress due to neutral current oscillations and parasitic inductance, leading to ringing and electromagnetic interference.
Innovation Solution
A system for a multi-phase power inverter using H-type multilevel power converters with a stacked or tiered arrangement of semiconductor switches, where positive, neutral, and negative buses are configured to minimize stray inductance and loop inductance through magnetic field cancellation, reducing parasitic inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If neutral point connection to stacked DC-link capacitor is used for zero voltage vector, then multilevel inverter can achieve high-voltage and high-power operation, but capacitor voltage imbalance and overvoltage stress occur due to neutral current oscillation
Solution Approach 1:
The patent divides the traditional single neutral point connection into multiple independent neutral points, one for each phase leg. This segmentation eliminates the common neutral current path that causes oscillation and voltage imbalance, while still enabling each phase to achieve zero voltage vector functionality independently.
Solution Approach 2:
The patent introduces independent neutral point connections as intermediary elements between each phase leg and the DC-link capacitor. These intermediaries isolate the neutral current paths, preventing the oscillation that would otherwise propagate through the common neutral point and cause voltage imbalance.
2Productivity
If multi-phase power inverter operates at higher switching frequencies, then power conversion efficiency improves, but parasitic inductance causes ringing and electromagnetic interference
Solution Approach 1:
The patent utilizes the magnetic field generated by the power loop current to cancel parasitic inductance effects. By strategically positioning conductors to create opposing magnetic fields, the harmful inductive reactance is counteracted, allowing high switching frequencies to operate without excessive ringing or EMI.
3Ease of manufacture
If conventional circuit topology is used, then circuit implementation is straightforward, but large power loop generates large parasitic inductance
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked configuration. By arranging power and return paths in different vertical layers, the power loop area is dramatically reduced, minimizing parasitic inductance while maintaining manufacturing feasibility through modular construction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in lower switching loss, reduced ringing, less electromagnetic interference, and lower device thermal stress, enhancing the performance and reliability of the power inverter.
Implementation Method 1
positive, neutral, and negative buses are configured to minimize stray inductance and loop inductance through magnetic field cancellation
Data Source
AI summary
A multi-phase power inverter for an electric propulsion system includes a plurality of H-type multilevel power converters arranged between a high-voltage DC power supply and an electric machine. Each of the plurality of H-type multilevel power converters is a solid-state integrated circuit (IC) that includes a positive DC power bus, a negative DC power bus, a neutral bus, and a plurality of semiconductor switches disposed in a stacked arrangement. The plurality of semiconductor switches is interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus.