Multi-Level Charge Transfer DAC With Sequenced Capacitor Switching
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Solution Overview
Problem
Conventional charge transfer digital-to-analog converters (DACs) used in sigma delta modulators require multiple capacitors and complex dynamic element matching sequences to achieve multi-level linearity, which increases complexity and power consumption, while existing solutions like two-phase charge transfer DACs are limited to fewer levels.
Innovation Solution
A multi-level charge transfer DAC design using a minimal number of capacitors and capacitive switch units with a sequencer to control switching sequences, allowing for the generation of N output levels by transferring charges proportional to the sum of capacitors, with alternative sequences for non-proportional levels and pseudo-random sequence shuffling to maintain linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional charge transfer DACs use multiple capacitors to achieve multi-level linearity, then the output resolution and linearity are improved, but the device complexity and power consumption increase
Solution Approach 1:
The DAC is divided into multiple stages, where each stage processes a subset of the digital input bits and generates a portion of the output levels. This segmentation allows the system to achieve high resolution (e.g., 16-bit) by combining the outputs of several lower-resolution stages, thereby reducing the complexity that would result from using a single large capacitor array.
Solution Approach 2:
Multiple capacitor arrays are nested within a hierarchical structure where smaller capacitor sets are contained within larger operational units. Each stage's capacitor array is designed to work in conjunction with the others, creating a nested architecture that achieves multi-level linearity without requiring all capacitors to be present simultaneously in a single stage.
2Measurement precision
If conventional charge transfer DACs use dynamic element matching sequences to achieve multi-level linearity, then the output accuracy is improved, but the switching complexity and power consumption increase
Solution Approach 1:
The patent employs periodic switching sequences that repeat over defined intervals, where capacitors are systematically connected and disconnected in a cyclical pattern. This periodic action ensures that over one complete cycle, the average charge transfer accurately represents the digital input value, achieving linearity without requiring complex non-repeating sequences.
Solution Approach 2:
The capacitor arrays and switching network are designed to automatically perform the charge redistribution and averaging functions required for linearity. The system self-regulates the switching sequences based on the digital input codes, eliminating the need for external complex control logic to manage dynamic element matching.
3Device complexity
If a two-phase charge transfer DAC is used, then the circuit simplicity is improved, but the output levels are limited to fewer levels
Solution Approach 1:
The patent extends the basic two-phase operation into multiple continuous phases or stages, where each phase contributes additional output levels. Instead of completing the conversion in two phases, the system continues the charge transfer and redistribution process through additional phases, maintaining the simplicity of phase-based operation while accumulating more discrete output levels across the extended sequence.
Solution Approach 2:
The system transitions from a single-stage two-phase approach to a multi-dimensional architecture combining multiple stages, each with its own capacitor arrays and switching sequences. This dimensional expansion allows the DAC to generate many more output levels (e.g., 16-bit resolution requiring 65,536 levels) while preserving the fundamental two-phase simplicity at each individual stage level.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a higher resolution DAC with more levels than conventional designs, maintaining linearity and reducing power consumption, while simplifying the circuitry and dynamic element matching, leading to more accurate sigma delta converters with improved stability and lower noise.
Implementation Method 1
each output level is defined by a different amount of electrical charge transferred to the output of the DAC. Thus, a charge transfer DAC is transferring charges
Data Source
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Figure 3A
AI summary
A digital-to analog converter (DAC) of the charge transfer type can be used in a sigma delta modulator for generating N output levels, wherein an output level is defined by a respective amount of charge transferred by the DAC. The DAC has a first capacitor switch unit receiving a reference voltage and a first digital input value to transfer first output charges, at least one second capacitor switch unit receiving the reference voltage and a second digital input value, wherein an output of the second capacitor switch unit is coupled in parallel with an output of the first capacitor switch unit to generate a sum of first and second transferred output charges; and a sequencer controlling switches of the first and second capacitor switch units wherein switching sequences according to individual first and second digital input values are provided for every DAC input value to generate the N output levels.