Switched-Capacitor Multi-Level DAC for Mismatch-Resistant Linearity
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Solution Overview
Problem
Multi-bit sigma-delta analog-to-digital converters face limitations in linearity due to capacitor mismatch and reference voltage variations in their digital-to-analog converters (DACs), which affect signal-to-noise and distortion ratio (SNDR) performance, especially at lower oversampling rates.
Innovation Solution
A method and system that map uniformly distributed input codes to non-uniformly distributed codes in a switched capacitor DAC, using a charge accumulator and multiple reference voltages to ensure each capacitor provides a proportional nominal charge, reducing the impact of capacitor mismatch and reference voltage asymmetry, thereby improving linearity without requiring dynamic element matching or calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-bit DAC is used instead of a single-bit DAC, then the oversampling ratio can be reduced, but the linearity performance deteriorates due to capacitor mismatch and reference voltage variations
Solution Approach 1:
The multi-bit input code is segmented into multiple sub-codes, each controlling a subset of capacitors. This segmentation allows the system to achieve multi-bit resolution while maintaining linearity by ensuring each capacitor is used for each sub-code value, making the output independent of capacitor matching.
Solution Approach 2:
The patent employs an asymmetric switching scheme where capacitors are connected to different reference voltages (Vref, -Vref, 0V) based on the sub-code values. This asymmetric voltage assignment, combined with the specific switching pattern, ensures that each capacitor contributes equally to the output regardless of its individual mismatch, thereby improving linearity.
2Manufacturing precision
If foreground calibration or background calibration techniques are used to improve DAC linearity, then linearity performance improves, but circuit complexity increases
Solution Approach 1:
The system achieves linearity improvement through its inherent switching architecture rather than external calibration circuits. The specific switching pattern and voltage assignment cause mismatched capacitors to contribute equally to each output level, making the DAC self-correcting for linearity errors without requiring additional calibration hardware or software.
Solution Approach 2:
The patent changes the operating parameters of the DAC by using multiple reference voltages (Vref, -Vref, 0V) and implementing a specific switching sequence. This parameter change transforms the system so that linearity is achieved through the switching architecture itself rather than through component matching or calibration.
3Manufacturing precision
If dynamic element matching techniques are used to improve linearity, then linearity performance improves, but device complexity and power consumption increase
Solution Approach 1:
The system achieves linearity through its inherent switching architecture rather than requiring dynamic element matching circuits. The switching pattern ensures that each capacitor is used for each code value, making the output independent of capacitor matching without needing additional DEM hardware.
Solution Approach 2:
The patent extracts the linearity improvement function from complex calibration or DEM circuits and embeds it directly into the basic switching architecture. By taking out the need for separate linearity correction mechanisms and integrating the solution into the fundamental operation, the system achieves high linearity with minimal complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the linearity of the DAC, allowing for higher output levels with fewer capacitors and reference voltages, maintaining high SNDR performance at lower oversampling rates and reducing the complexity and power consumption of the converter.
Implementation Method 1
transferred a first charge from a set of DAC capacitors to a charge accumulator based on the MSC; and transferred a second charge from the set of DAC capacitors to the charge accumulator based on the LSC
Data Source
AI summary
In accordance with an embodiment, a method for digital-to-analog conversion includes: mapping a uniformly distributed input code to a non-uniformly distributed input code of a switched capacitor digital-to-analog converter (DAC), the non-uniformly distributed input code including a most significant code (MSC) and a least significant code (LSC); transferring a first charge from a set of DAC capacitors to a charge accumulator based on the MSC; forming a second charge based on the LSC; and transferring the second charge from the set of DAC capacitors to the charge accumulator, where each capacitor of the set of DAC capacitors is used for each value of the non-uniformly distributed input code, each capacitor of the set of DAC capacitors provides a same corresponding nominal charge within each value of the non-uniformly distributed input code, and where the same nominal charge is proportional to a value of the non-uniformly distributed input code.