Multilevel DC/DC Converter With Polygon Capacitors for Low-Loss Switching
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Solution Overview
Problem
Existing DC/DC converters face limitations in switching characteristics and efficiency, particularly at higher frequencies, due to high breakdown voltage requirements and single-phase technology, which leads to increased losses and ripple issues.
Innovation Solution
A DC/DC converter utilizing multilevel technology with a transformer and polygon-connected resonance capacitors, incorporating a multilevel converter and control circuit to manage phase shifting and resonance, allowing for lower voltage semiconductors and reduced losses, and enabling multiphase operation for ripple cancellation and constant power flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If 2-level half bridges are used in DC/DC converters, then the converter structure is simple, but the switching losses increase and efficiency decreases at higher frequencies
Solution Approach 1:
The patent applies segmentation by dividing the voltage levels into multiple stages using multilevel converter technology. Instead of using a single 2-level half bridge, the converter is segmented into multiple levels (3-level, 5-level, or 7-level) where each stage handles a portion of the voltage conversion. This segmentation reduces the voltage stress on individual semiconductor devices and decreases switching losses at higher frequencies, directly resolving the contradiction between structural simplicity and energy efficiency.
2Strength
If higher breakdown voltage semiconductors are used, then the converter can handle higher voltages, but the figure of merit (RdsonxQ) deteriorates and losses increase
Solution Approach 1:
The multilevel converter architecture segments the high voltage into multiple lower voltage levels. Each semiconductor device only needs to block a fraction of the total voltage (e.g., Udc/3 for 3-level, Udc/5 for 5-level, Udc/7 for 7-level), allowing the use of lower breakdown voltage devices with superior RdsonxQ figures of merit. This directly reduces conduction losses while maintaining the ability to handle high input voltages through the series combination of multiple lower-voltage devices.
Solution Approach 2:
The patent changes the voltage parameter distribution across semiconductor devices by introducing multiple voltage levels. Instead of requiring each device to withstand the full input voltage, the voltage stress is redistributed across multiple devices operating at lower voltage levels. This parameter change enables the selection of semiconductors with optimal RdsonxQ characteristics for the reduced voltage stress, thereby minimizing conduction losses.
3Device complexity
If single-phase technology is used, then the converter design is straightforward, but ripple cancellation is insufficient and power flow is not constant
Solution Approach 1:
The patent merges multiple phase legs (typically 3 or more) in parallel configuration, where each leg operates with a phase shift relative to others. The output currents from multiple phases are combined at the output capacitor, achieving ripple cancellation through the interleaved switching patterns. This merging of multiple phases provides constant power flow from input to output and significantly reduces output voltage ripple, resolving the contradiction between design simplicity and ripple cancellation performance.
Solution Approach 2:
The patent employs periodic phase-shifted switching patterns across multiple legs. Each leg operates with a specific phase shift (e.g., 120° for 3-phase, 90° for 4-phase), creating periodic current waveforms that complement each other. The combined effect of these periodic actions results in ripple cancellation at the output, as the peaks and valleys of individual phase currents offset each other, providing constant power flow and reduced ripple without requiring complex control algorithms.
4Device complexity
If star connection of resonance capacitors is used, then the circuit configuration is simple, but current stress on capacitors increases
Solution Approach 1:
The patent transitions from the symmetric star connection to an asymmetric polygon (delta) connection of resonance capacitors. In the polygon connection, each capacitor is connected between adjacent phase legs, forming a closed loop. This asymmetric configuration distributes the current stress more evenly across all capacitors and eliminates the neutral point current that would otherwise concentrate stress on individual capacitors in the star connection. The polygon connection maintains circuit simplicity while significantly reducing capacitor current stress and improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances switching characteristics, reduces losses, and provides improved efficiency by utilizing lower breakdown voltage semiconductors and multiphase technology, achieving 0 AC ripple and constant power flow, while maintaining reliability through polygon capacitor connections.
Implementation Method 1
a transformer that comprises a primary side and a secondary side, wherein the primary side comprises a number of n primary coils and the secondary side comprises a number of n secondary coils
Implementation Method 2
The DC/DC-converter according to the invention comprises a transformer that comprises a primary side and a secondary side... a first converter circuit that is connected in between the primary side of the transformer and two primary side contacts, the first converter circuit comprising a first multilevel converter
Data Source
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AI summary
DC/DC-Converter (1), comprising a transformer (2) that comprises a primary side (2a) and a secondary side (2b), wherein the primary side (2a) comprises a number of n primary coils (3a, 3b, 3c) and the secondary side (2b) comprises a number of n secondary coils (4a, 4b, 4c), wherein the primary side (2a) of the transformer (2) is terminated by a number of n primary capacitors (5a, 5b, 5c), which are connected in a first polygon arrangement (5), each of the primary capacitors (5a, 5b, 5c) connecting two of the primary coils (4a, 4b, 4c), a first converter circuit (6) that is connected in between the primary side (2a) of the transformer and two primary side contacts (8a, 8b), the first converter circuit (6) comprising a first multilevel converter, that is configured to work as a inverter when the DC/DC-converter (1) is used in a forward mode, wherein the first multilevel converter is configured to receive a DC input current that is provided to the primary side contacts (8a, 8b) and to provide n-phases of an alternating current to the n primary coils (3a, 3b, 3c) of the transformer (2), respectively, a second converter circuit (7) that is connected in between the secondary side (2b) of the transformer (2) and two secondary side contacts (9a, 9b) and is configured to work as a rectifier when the DC/DC-converter (1) is used in a forward mode, wherein the second converter circuit (7) is configured to receive an alternating current from each of the n secondary coils (4a, 4b, 4c) of the transformer (2), and to provide a DC output current to the secondary side contacts (9a, 9b), and a control circuit (10) that is configured to control the first multilevel converter of the first converter circuit (6) to work as the inverter in the forward mode.