Multilevel DRAM Readout Using Amplifier Offset Sensing
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Solution Overview
Problem
Existing integrated circuit memories face challenges in storing multiple bits per cell without increasing read cycle time, compromising clock speed, and maintaining power efficiency, particularly in Dynamic Random Access Memories (DRAMs) as they shrink in dimensions and bit lines lengthen, reducing read signal margins.
Innovation Solution
A new read method for multilevel DRAMs that introduces an intentional offset in amplifiers to sense data states, allowing fast identification of multiple bits per cell by precharging bit lines, nulling amplifier offsets, and adjusting amplifier offsets to distinguish voltage levels without altering the differential voltage between bit and reference lines, followed by rewriting the data back into the memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multilevel memory stores more than one bit per memory cell, then memory capacity increases, but read cycle time increases and clock speed must be reduced
Solution Approach 1:
The read operation is divided into two sequential phases: first bit reading and second bit reading. The first bit is read using conventional sense amplifiers, then the second bit is read using modified sense amplifiers with adjusted reference voltages. This segmentation allows each phase to be optimized independently, enabling multilevel storage without excessive read cycle time penalty.
Solution Approach 2:
Reference voltages for the second bit reading operation are established during the first bit reading phase. The sense amplifiers are configured with appropriate reference voltages before the second bit reading begins, eliminating the need for additional voltage setup time and reducing overall read cycle time.
2Area of moving object
If DRAM shrinks in dimensions to increase density, then more memory cells fit in smaller space, but read signal margins decrease due to longer bit lines and smaller capacitance
Solution Approach 1:
Different sense amplifiers are used for different reading operations: conventional sense amplifiers for the first bit and modified sense amplifiers with adjusted reference voltages for the second bit. This local differentiation allows optimization of signal margins for each specific reading task, compensating for the reduced signal margins caused by smaller cell sizes and longer bit lines.
Solution Approach 2:
The reference voltages of the sense amplifiers are dynamically adjusted based on the reading operation. For the second bit reading, reference voltages are modified to account for the reduced signal margins, thereby maintaining reliable detection despite the smaller memory cell dimensions and longer bit lines.
3Ease of operation
If conventional read methods are used for multilevel memory, then simple reading is achieved, but power consumption increases due to frequent refreshing and extended read cycles
Solution Approach 1:
The read operation maintains continuous useful action by performing both bit readings within a single coherent cycle without requiring interruption for voltage reconfiguration. The sense amplifiers are kept powered and configured throughout the process, eliminating idle periods and reducing overall power consumption compared to sequential operations with power cycling.
Data Source
AI summary
The present invention includes apparatus and a method for reading one or more data states from an integrated circuitry memory cell, including the steps of connecting the memory cell to a bit line which is connected to an amplifier having an offset control which introduces an offset during the sensing portion of a read cycle to identify a data state stored in the memory cell.