Multilevel Driver Slices for Noise-Resilient Chip-to-Chip Links
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Solution Overview
Problem
Current high-speed chip-to-chip communication systems face challenges in achieving high bandwidth, low latency, and low power consumption while maintaining resilience to noise and crosstalk, particularly in multi-chip systems where pin efficiency and power utilization are critical.
Innovation Solution
The implementation of a multilevel driver using vector signaling codes, such as the H4 and 5b6w codes, which transmit data over multiple wires with multiple voltage levels, and a multi-phase processing architecture to optimize signal transmission, ensuring high bandwidth and low power consumption, while using matched impedance transmission lines to minimize noise and crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional binary signaling is used for chip-to-chip communication, then the system is simpler to implement, but the bandwidth and pin efficiency are limited
Solution Approach 1:
The patent changes the signaling parameter from binary (2 levels) to multilevel (4 or more voltage levels), allowing multiple bits to be transmitted per symbol period. This increases bandwidth by a factor of log2(M) where M is the number of levels, while the complexity increase is managed through structured coding schemes like H4 and 5b6w codes.
Solution Approach 2:
The patent transitions from single-wire serial transmission to multi-wire parallel transmission with vector signaling. By adding spatial dimension (multiple wires) and combining with multilevel signaling, the system achieves higher bandwidth while maintaining pin efficiency through coordinated signal transmission across multiple channels.
2Speed
If higher transmission speeds are achieved, then bandwidth increases, but noise resilience and crosstalk become more significant problems
Solution Approach 1:
The patent converts the harmful effect of crosstalk into a beneficial feature by designing balanced vector signaling codes where the sum of signals across multiple wires is constrained to zero. This balancing technique causes crosstalk and common-mode noise to cancel out, improving noise resilience while enabling higher transmission speeds.
Solution Approach 2:
The patent incorporates feedback mechanisms through balanced signaling constraints, where the receiver can detect violations of the balancing condition and use this information to correct errors. The structured coding schemes provide inherent error detection and correction capabilities that improve reliability at high speeds.
3Productivity
If more pins are used for parallel transmission, then bandwidth increases, but pin efficiency decreases
Solution Approach 1:
The patent merges multiple functions into a single pin by implementing multilevel signaling that transmits multiple bits per symbol period. Instead of dedicating one pin per bit, M pins transmit log2(M) bits each simultaneously, reducing the total pin count while maintaining high bandwidth through coordinated multilevel vector signaling.
Solution Approach 2:
Each transmission pin serves multiple functions by carrying multilevel signals that encode multiple bits of information. The pins are universally utilized to transmit data, control signals, and maintain balancing constraints, maximizing pin efficiency through sophisticated signal encoding schemes.
4Productivity
If multilevel signaling is implemented to increase bandwidth, then pin efficiency improves, but power consumption increases
Solution Approach 1:
The patent uses partial action by implementing controlled signal switching where not all signal levels are used equally at all times. The balanced vector signaling codes distribute signal transitions across multiple wires and time periods, reducing the instantaneous power demand while maintaining average pin efficiency through optimized signal sequences.
Data Source
AI summary
A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.