Multilevel Encoding Circuit With Time-Switched FEC for 64-QAM Noise Tolerance

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Solution Overview

Problem

Existing optical transmission systems face challenges in reducing power consumption without compromising noise tolerance, particularly when using multilevel modulation techniques like 64 QAM, where the normal MLC method reduces noise tolerance due to limitations in error correction code processing.

Innovation Solution

The proposed solution involves an encoding circuit that switches between inserting error correction codes in different time periods, using a combination of hard decision (HD)-FEC and soft decision (SD)-FEC parities across bit strings, optimizing the allocation of symbols in the constellation to maintain noise tolerance while reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If normal MLC method is used for error correction coding, then power consumption is reduced, but noise tolerance deteriorates

Engineering Contradiction:
Improvepower consumptionVSAvoidnoise tolerance
Core Design Contradiction:
Use of energy by stationary objectVSReliability

Solution Approach 1:

The patent applies dynamics by making the error correction coding method time-variant. The encoding circuit switches between normal MLC method (for power saving) and enhanced MLC method (for noise tolerance) based on temporal conditions. This dynamic switching allows the system to adapt its error correction strategy over time, achieving both power efficiency and noise tolerance by using different coding approaches at different time periods.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements periodic action through cyclic switching between two error correction coding modes. The encoding circuit alternates between inserting enhanced MLC parity bits (which provide better noise tolerance) and normal MLC parity bits (which consume less power). This periodic alternation ensures that the system maintains adequate noise tolerance while minimizing overall power consumption, as the enhanced method is used only periodically rather than continuously.

Inventive Principle:
Principle #19Periodic action

2Reliability

If enhanced MLC method is used for error correction coding, then noise tolerance is improved, but power consumption increases

Engineering Contradiction:
Improvenoise toleranceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent applies partial action by using the enhanced MLC method only partially rather than continuously. Specifically, the encoding circuit uses the enhanced MLC method with additional parity bit insertion only during certain time periods (e.g., when noise tolerance requirements are higher), while using the normal MLC method during other periods. This partial application of the enhanced method achieves adequate noise tolerance protection without incurring the full power consumption cost of continuous enhanced coding.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If error correction code is inserted in all bit strings, then noise tolerance is improved, but device complexity increases

Engineering Contradiction:
Improvenoise toleranceVSAvoidencoding circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by differentiating the error correction approach for different bit strings based on their significance. The encoding circuit identifies a first significant bit string and applies enhanced error correction (with additional parity bits) specifically to this bit string, while using normal error correction for other less critical bit strings. This localized enhancement provides improved noise tolerance for the most important data without unnecessarily increasing complexity for all bit strings.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11431354B2Encoding circuit, decoding circuit, encoding method, decoding method, and transmitting device
Publication Date: 2022.08.30 FUJITSU LTD
  • US11431354B2 patent drawing
  • US11431354B2 patent drawing
  • US11431354B2 patent drawing

AI summary

An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit stings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.