Multilevel Flash Memory Error Correction Using Symbol-Level Coding
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Solution Overview
Problem
Existing data processing systems for multilevel flash memory face inefficiencies in error correction, leading to storage overhead and latency due to the need for extensive error correcting codes and complex mechanisms, which reduce storage capacity and performance.
Innovation Solution
Implementing error correcting circuitry that matches error correction mechanisms to the symbol error properties of multilevel flash memory cells, using techniques like Reed Solomon codes and precoding to increase error correction efficiency and reduce redundant storage and hardware overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction mechanisms are used for multilevel flash memory, then data integrity is maintained, but storage capacity is reduced due to extensive error correcting codes and hardware overhead
Solution Approach 1:
The patent changes the parameter of error correction by transitioning from traditional bit-level error correction to symbol-level error correction. Each symbol represents multiple bits (e.g., 2 bits per symbol for 4 voltage levels), and error correction is performed on symbols rather than individual bits. This parameter change reduces the number of error correction code symbols needed, thereby increasing storage capacity while maintaining data integrity through symbol-based correction mechanisms
2Reliability
If traditional error correction mechanisms are used for multilevel flash memory, then data integrity is maintained, but system performance degrades due to latency and complex mechanisms
Solution Approach 1:
The patent changes the operational parameter from bit-level processing to symbol-level processing in error correction. By treating groups of bits as symbols that correspond to specific voltage levels, the error correction process operates on larger units more efficiently. This reduces the computational complexity and number of operations required, thereby decreasing latency and improving system performance while maintaining data integrity
Solution Approach 2:
The patent segments the error correction process into symbol-based operations rather than bit-level operations. By dividing the data into symbols that represent multiple bits each, and applying error correction at the symbol level, the system reduces the overall complexity of the correction mechanism. This segmentation approach simplifies the error correction pathway and reduces processing time, improving system performance
Data Source
AI summary
An integrated circuit is provided with an array of multilevel flash memory cells. In one embodiment these flash memory cells have a storage signal level which is Gray coded to output data bits thereby increasing the independence between bit errors. The error correction circuitry targets independent identical distributed error patterns. In another embodiment, the storage signal levels are read to generate n-bit symbols which are then subject to error correction with an error correction mechanism targeted at the error properties of those n-bit symbols. The data is read in sets of symbols such that the error correction targeted at those symbols will be more efficient.