Multi-Level FSM Modulation Coding for Long Transition Run Suppression

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Solution Overview

Problem

Existing methods for eliminating long transition runs in magnetic recording channels, such as maximum transition run (MTR) codes, suffer from channel density penalties and performance degradation due to code rate loss.

Innovation Solution

A multi-level finite state machine (ML-FSM) with a periodic structure is used for modulation coding, incorporating penalty-free and penalty edges to connect nodes within and across time frames, effectively suppressing long transition runs and shaping transition distributions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If MTR codes are used to eliminate long transition runs, then transition run length is reduced, but code rate is limited and channel density penalty occurs

Engineering Contradiction:
Improvelong transition runsVSAvoidcode rate
Core Design Contradiction:
Object-affected harmful factorsVSProductivity

Solution Approach 1:

The patent transitions from conventional binary FSM to multi-level FSM, adding an extra dimension (levels) to the state machine structure. This allows the system to suppress long transition runs while maintaining higher code rates by utilizing multiple levels (0 to L-1) instead of just binary states, effectively resolving the contradiction between transition run suppression and code rate maintenance

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the fundamental parameter of the FSM from binary (2 states) to multi-level (L states), where L > 2. This parameter change enables the system to achieve both long transition run suppression and higher code rates by adjusting the number of levels and using dropping edges to reset accumulated penalties periodically

Inventive Principle:
Principle #35Parameter changes

2Reliability

If MTR codes are used to suppress long transition runs, then transition distribution is improved, but performance degradation occurs due to code rate loss

Engineering Contradiction:
Improveerror rate performanceVSAvoidcode rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By introducing multiple levels in the FSM structure, the patent enables better transition distribution control while maintaining higher code rates. The multi-level structure provides more flexibility in shaping transition distributions compared to binary FSM, thereby improving error rate performance without sacrificing code rate

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements periodic dropping edges that reset accumulated penalties at regular intervals (every N time frames). This periodic action prevents permanent penalty accumulation and allows the system to maintain higher average code rates while still achieving good transition distribution and error rate performance

Inventive Principle:
Principle #19Periodic action

3Object-affected harmful factors

If conventional FSM with redundant DC nodes is used, then long transitions are suppressed, but code rate is limited

Engineering Contradiction:
Improvelong transition runsVSAvoidcode rate
Core Design Contradiction:
Object-affected harmful factorsVSProductivity

Solution Approach 1:

The patent extends conventional FSM by adding a level dimension, transforming it from a single-level structure to a multi-level periodic structure. This dimensional extension allows the system to suppress long transition runs through penalty mechanisms while maintaining higher code rates by utilizing the additional level space for data encoding

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces dynamic penalty accumulation and resetting mechanisms where penalties are accumulated during penalty edges and periodically reset by dropping edges. This dynamic behavior allows flexible control of transition run suppression while adapting to maintain optimal code rates, unlike static conventional FSM structures

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8730067B2Optimized multi-level finite state machine with redundant DC nodes
Publication Date: 2014.05.20 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8730067B2 patent drawing
  • US8730067B2 patent drawing
  • US8730067B2 patent drawing

AI summary

A method and system for eliminating/suppressing long transition runs over a communications channel is disclosed. The method may include providing modulation coding based on a multi-level finite state machine (ML-FSM) having a periodic structure, the periodic structure being defined by a predetermined number of time frames. The ML-FSM may include a plurality of penalty-free edges for connecting nodes in one time frame to nodes at the same level in a subsequent time frame and a plurality of penalty edges for connecting nodes in one time frame to nodes at an upper level in the subsequent time frame. The method may further include utilizing the ML-FSM based modulation coding to facilitate data transmission over the communications channel.