Multilevel Gate Electrode for 3D Memory Transistor Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for manufacturing field effect transistors in three-dimensional semiconductor devices, such as vertical NAND strings, require additional processing steps and occupy significant device area, making them inefficient for compact memory structures.
Innovation Solution
A method that integrates the formation of switching transistors and memory devices using the same set of processing steps, where memory openings and device openings are formed simultaneously, and electrically conductive layers are isolated to provide independently controlled control gate electrodes, allowing for compact and efficient integration within three-dimensional memory structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If field effect transistors are manufactured using existing methods in three-dimensional semiconductor devices, then the transistors can be formed, but additional processing steps are required and significant device area is occupied
Solution Approach 1:
The patent merges the formation of field effect transistors and memory devices into a single integrated structure. The gate electrode serves dual purposes: as the control gate for the field effect transistor and as the control gate for the memory device, eliminating the need for separate transistor fabrication steps and reducing overall device area
Solution Approach 2:
The gate electrode is designed to perform multiple functions simultaneously - it acts as both the control gate for switching operations and the control gate for memory operations. This multi-functionality allows a single structure to replace what would traditionally require separate components, reducing processing complexity and area requirements
2Area of stationary object
If field effect transistors are integrated within three-dimensional memory structures, then area requirements are reduced, but independent control over memory device operations must be maintained
Solution Approach 1:
The gate electrode is segmented into multiple levels along the vertical channel, with each level independently controllable. This segmentation allows different portions of the gate to independently control different regions of the memory device, maintaining operational independence while achieving compact integration within the three-dimensional structure
Data Source
Figure 1
Figure 2A~2B
Figure 2C~2D
AI summary
A switching field effect transistor and the memory devices can be formed employing a same set of processing steps. An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures for memory devices and gate dielectric - channel structures for the field effect transistor can be simultaneously formed in a memory region and in a transistor region, respectively. After replacement of the sacrificial material layers with electrically conductive layers, portions of the electrically conductive layers in a memory region are electrically isolated from one another to provide independently controlled control gate electrodes for the memory devices, while portions of the electrically conductive layers in the transistor region are electrically shorted among one another to provide a single gate electrode for the switching field effect transistor.