Multilevel IC Interconnect Routing for Flexible Via Alignment
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Solution Overview
Problem
Current self-aligned via schemes for back end of line (BEOL) connections in integrated circuits face challenges with alignment accuracy, limited routing capabilities, and the need for precise alignment between via and bottom metal layers, which can lead to short circuits with neighboring lines.
Innovation Solution
The proposed solution involves a multilevel routing track system in integrated circuits, where conductive lines extend in parallel across at least three levels: a lower extension line level, a centerline level, and an upper extension line level. This design allows for flexible connection between lines at different levels, increasing routing possibilities without adding metal and via layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional self-aligned via schemes are used to ensure alignment between via and top metal, then alignment precision is improved, but routing flexibility deteriorates due to limited routing capabilities and inability to optimize R/C parameters
Solution Approach 1:
The patent introduces a vertical dimension to routing by implementing multilevel routing tracks within a single metal layer. Conductive parts are arranged at different heights (lower extension line level, centerline level, upper extension line level) allowing signals to route vertically within the layer, effectively adding a third dimension to the traditionally planar routing space. This enables flexible routing paths without requiring additional metal layers or vias.
Solution Approach 2:
The patent segments the routing function across multiple vertical levels within a single metal layer. Instead of having all conductive lines at one height, the routing track is divided into lower extension line level, centerline level, and upper extension line level. This segmentation allows independent optimization of each level for specific routing needs while maintaining alignment through coplanar sidewalls.
2Adaptability or versatility
If additional metal and via layers are added to increase routing capabilities, then routing flexibility is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent makes a single metal layer perform multiple routing functions that traditionally required separate layers. By implementing multilevel routing tracks within one metal layer, the same layer can provide both horizontal interconnects and vertical routing paths, effectively making the metal layer universal for both signal routing and alignment reference purposes.
Solution Approach 2:
The patent exploits the vertical dimension within a single metal layer to create multiple routing levels. By arranging conductive parts at different heights (lower extension line level, centerline level, upper extension line level) with coplanar sidewalls, the invention effectively packs three levels of routing capability into what would traditionally be a single-planar layer, eliminating the need for additional metal layers.
3Reliability
If VIA mask alignment is made more precise to avoid short circuits with neighboring lines, then reliability is improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent implements self-alignment through coplanar sidewalls of conductive parts at different levels. The lower extension line level, centerline level, and upper extension line level are all self-aligned through their shared coplanar sidewalls, eliminating the need for complex mask alignment procedures. The structure automatically aligns itself during fabrication, making the process as simple as standard self-aligned via formation.
Data Source
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AI summary
Integrated circuit comprising an interconnection system comprising at least one multilevel layer comprising first parallel electrically conductive lines (20, 21, 22, 23), said multilevel layer comprising at least three levels (L0, L1, L2) forming a centerline level (L1), an upper extension line level (L2) and a lower extension line level (L0) said levels providing multilevel routing tracks in which said lines extend.