Multi-Level Lateral DRAM Capacitors for Collapse-Resistant Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor fabrication technology advances, the reduced size of DRAM memory cells increases the risk of collapse or wobbling during manufacturing, necessitating improvements in capacitor structure and manufacturing methods to enhance strength and stability.
Innovation Solution
The manufacturing method involves creating capacitors that extend laterally over the semiconductor substrate, with capacitors arranged in different levels and configured in parallel, using a semiconductor substrate with insulating and dielectric layers, and electrodes made of tungsten, to prevent collapse and allow for parallel electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of DRAM memory circuits is reduced to a few nanometers, then the integration density is improved, but the structural strength deteriorates causing collapse or wobbling
Solution Approach 1:
The capacitor structure transitions from a conventional vertical configuration to a lateral configuration where the capacitor extends in the lateral direction rather than vertically. This dimensional change allows the capacitor to achieve sufficient structural strength while maintaining high integration density through multi-level stacking of capacitors at different lateral positions
Solution Approach 2:
Multiple capacitors are nested at different levels with varying lateral lengths. Longer capacitors are positioned at lower levels while shorter capacitors are positioned at higher levels, creating a nested arrangement that maximizes space utilization and maintains structural integrity at reduced dimensions
2Ease of manufacture
If capacitors are configured in different lengths and levels laterally, then the manufacturing complexity is reduced, but the device complexity increases
Solution Approach 1:
The capacitor array is segmented into multiple groups, with each group containing capacitors of identical lateral length. This segmentation allows capacitors within each group to be manufactured using the same process parameters, simplifying manufacturing while the overall device achieves high density through the coordinated arrangement of multiple segmented groups at different levels
Data Source
AI summary
The present application provides a method of manufacturing a memory device. The method includes steps of providing a semiconductor substrate; disposing a first insulating layer over the semiconductor substrate; disposing a first bottom electrode over the first insulating layer; disposing a first dielectric layer over the first bottom electrode; removing a portion of the first dielectric layer to form a first recess extending through the first dielectric layer; disposing a first capacitor dielectric conformal to the first recess and over the first bottom electrode; and forming a first top electrode within the first recess and surrounded by the first capacitor dielectric, wherein the first capacitor dielectric and the first top electrode extend laterally over the first bottom electrode and the semiconductor substrate.