Multilevel Memory Bus System for Scalable NAND Flash Performance
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Solution Overview
Problem
Existing memory bus designs for solid-state storage devices face challenges in increasing memory capacity without impacting performance or data integrity, and are not readily adaptable to advancements in semiconductor technology.
Innovation Solution
A multilevel memory bus system that includes a DMA controller, an intermediate bus, a flash memory bus, and a flash buffer circuit, supporting configurable bus widths, data sampling rates, CRC protection, and exclusive busy mechanisms to maintain performance and data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity of solid-state memory subsystems is increased, then storage capacity is improved, but memory performance deteriorates
Solution Approach 1:
The memory subsystem is segmented into multiple independent memory channels, each with its own dedicated memory bus interface. This allows the system to scale capacity by adding more channels without saturating a single bus, thereby maintaining performance while increasing storage capacity.
Solution Approach 2:
The patent transitions from a single-dimension memory bus architecture to a multi-dimensional architecture with multiple channels operating in parallel. This dimensional expansion allows simultaneous data transfers across multiple channels, preventing performance degradation as capacity increases.
2Quantity of substance
If memory capacity of solid-state memory subsystems is increased, then storage capacity is improved, but data integrity deteriorates
Solution Approach 1:
By dividing the memory subsystem into separate channels with dedicated interfaces, the system isolates potential data integrity issues to individual channels. This segmentation prevents errors from propagating across the entire memory subsystem, maintaining overall data integrity as capacity scales.
Solution Approach 2:
The patent introduces intermediate control logic and status monitoring at each channel interface, acting as mediators that detect and manage data integrity issues. These intermediaries ensure that capacity expansion does not compromise the reliability of data transfers.
3Productivity
If known memory bus designs are used, then current performance requirements are met, but adaptability to semiconductor technology advancements deteriorates
Solution Approach 1:
The memory bus interface is designed with dynamic configurability, allowing parameters such as bus width, data rate, and channel count to be adjusted based on the specific semiconductor memory devices being used. This dynamic adaptation enables the system to leverage technology advancements without requiring complete redesign.
Solution Approach 2:
The patent employs parameter-based configuration where key bus characteristics (width, speed, timing) can be modified to match different generations of semiconductor memory technology. This parameter flexibility allows the same basic architecture to remain performant across evolving technology landscapes.
4Device complexity
If fixed bus width is used, then design simplicity is maintained, but flexibility in memory capacity configuration deteriorates
Solution Approach 1:
The memory bus interface is designed as a universal platform that can accommodate multiple bus widths and configurations through a single adaptable architecture. This multi-functionality allows the system to support various memory capacity configurations without requiring separate dedicated designs for each scenario.
Data Source
AI summary
The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.