Multi-Level Memory Channel Block Coding
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Solution Overview
Problem
Current multi-level flash memory technologies face challenges in distinguishing between adjacent signal levels, leading to reduced signal distance and limitations in the number of signal levels that can be reliably written and read, which restricts memory density and storage capacity.
Innovation Solution
A memory apparatus with a channel block and controller that employs high gain coding schemes such as pulse amplitude modulation, quadrature amplitude modulation, low density parity check codes, and trellis coded modulation to effectively distribute and decode multi-level signals, reducing overlap and improving signal detection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level signals are used to increase memory capacity, then storage density is improved, but signal distance and reliability deteriorate
Solution Approach 1:
The patent applies parameter changes by transitioning from traditional binary signaling to multi-level signaling schemes (such as 4-level or 8-level signals). This changes the signal parameter from 2 states to multiple states, allowing more bits to be stored per cell. The patent specifically implements this through coded modulation techniques that distribute signal levels strategically to maintain reliability while increasing capacity.
Solution Approach 2:
The patent uses composite coding schemes that combine multiple coding techniques (such as concatenating outer Reed-Solomon codes with inner convolutional or LDPC codes). This composite approach integrates different coding methods to simultaneously achieve high storage density and maintain signal reliability through error correction capabilities.
2Quantity of substance
If the number of signal levels is increased beyond four, then storage capacity is improved, but signal level distinction and detection reliability worsen
Solution Approach 1:
The patent implements feedback mechanisms through iterative decoding processes. The receiver uses feedback from detected signal levels to adjust and refine the interpretation of subsequent signals. This is achieved through iterative decoding algorithms that continuously improve signal level distinction by using information from previous detections to inform current readings, thereby maintaining measurement precision even with higher signal levels.
Solution Approach 2:
The patent applies preliminary action through pre-coding and training sequences before actual data transmission. Reference signals and training sequences are transmitted first to establish baseline signal characteristics and calibration information. This preliminary action enables the receiver to adapt to the specific multi-level signal characteristics before actual data is written or read, improving signal level distinction reliability.
3Device complexity
If simple prior art slicer circuits are used for signal detection, then device complexity is reduced, but the number of reliable signal levels is limited
Solution Approach 1:
The patent replaces traditional mechanical or analog slicer circuits with digital signal processing and software-based decoding algorithms. Instead of using fixed analog threshold circuits, the invention employs digital processors that can dynamically adjust to multi-level signals through programmed algorithms. This substitution enables support for more signal levels while keeping the physical circuit complexity manageable through programmability.
Solution Approach 2:
The patent implements universal decoding architectures that can handle multiple signal levels through a single flexible processing unit. The controller and channel block are designed to be multi-functional, capable of adapting to different signaling schemes (4-level, 8-level, or other configurations) without requiring dedicated hardware for each level. This universality allows the system to increase the number of signal levels while maintaining reasonable device complexity through software-defined functionality.
Data Source
AI summary
Embodiments of the present invention provide high density, multi-level memory. Thus, various embodiments of the present invention provide a memory apparatus in accordance with various embodiments of the present invention includes a memory block comprising a plurality of cells, each cell adapted to operate with multi-level signal. Such a memory apparatus also includes a channel block adapted to code data values in accordance with a coding scheme that favorably effects a distribution of the multi-levels of the multi-level signals, and to output the corresponding multi-level signals of the coded data values to the memory block. Other embodiments may be described and claimed.