Multi-Level Memory Defect Analysis via Hierarchical Pattern Classification
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Solution Overview
Problem
Conventional defect analysis systems are inadequate for multi-level memory cell devices and embedded multi-level memory in system-on-chip integrated circuits, as they fail to effectively identify and manage the complex failure mechanisms in these advanced semiconductor products, leading to lower yield and profitability.
Innovation Solution
A multi-level memory defect analysis system and method that automatically classifies failed bits and patterns, generates interpretable reports, and provides three-dimensional classification, correlation with other data sources, zonal analysis, redundancy implementation, and reconfiguration of memory device capacity, enabling more effective quality control and yield management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional binary mode defect analysis is used for multi-level memory cells, then the analysis system remains simple and easy to operate, but it fails to identify complex failure mechanisms and patterns in multi-level memory devices
Solution Approach 1:
The patent segments defect analysis into multiple classification levels: first separating pass/fail status, then further categorizing failed cells by pattern type (e.g., row, column, block, random), and finally classifying by failure mechanism. This hierarchical segmentation enables comprehensive multi-level memory analysis while maintaining system manageability through structured organization of complexity.
Solution Approach 2:
The patent transitions from conventional binary (pass/fail) analysis to multi-dimensional classification by adding dimensions such as failure patterns, affected memory levels, and spatial distributions. This dimensional expansion allows the system to capture complex failure mechanisms in multi-level memory cells while organizing the increased complexity into structured categories.
2Productivity
If multi-level memory defect analysis with comprehensive classification is implemented, then yield management improves through better defect identification, but the analysis tool complexity increases significantly
Solution Approach 1:
The patent creates a universal analysis framework that handles multiple memory types (standard memory, multi-level memory, embedded memory) and various failure patterns through a single integrated system. The tool performs multiple functions including defect classification, pattern recognition, yield analysis, and root cause identification, consolidating what would otherwise require separate specialized tools into one multi-functional platform.
Solution Approach 2:
The patent utilizes parameter changes in memory cell states (different charge levels in multi-level cells) as classification criteria. By analyzing variations in electrical parameters such as threshold voltage shifts and charge retention levels across multiple states, the system identifies failure patterns and mechanisms while organizing complexity through parameter-based categorization.
3Reliability
If detailed defect classification and pattern analysis are performed on multi-level memory, then the ability to identify failure mechanisms improves, but the time and computational resources required increase
Solution Approach 1:
The patent performs preliminary classification of failed cells by obvious pattern types (row, column, block failures) and straightforward failure mechanisms first. This preliminary action quickly identifies and categorizes common failure modes, allowing the system to focus computational resources on more complex cases that require detailed multi-parameter analysis, thereby reducing overall analysis time.
Solution Approach 2:
The patent creates standardized classification templates and pattern libraries that can be reused across different memory devices and defect types. Once failure patterns are identified and classified, the system stores these as reference copies that can be rapidly matched against new defects, reducing analysis time for recurring failure modes while maintaining detailed classification capabilities.
Data Source
AI summary
A system and method for defect analysis of multi-level memory cell devices and embedded multi-level memory in system-on-chip integrated circuits are disclosed wherein a defect data set is input into the system. When a defect data set is received, an automated test engineering system running a memory test program analyzes the defect data set to generate one or more fail bit locations and one or more fail states of the memory. The multi-level memory defect analysis system and method then classify failed bits or patterns comprising a vertical fail pattern, whereby after being classified, each memory cell failure vertical fail pattern has three data attributes comprising fail type, a number of fail bits/states, and a sequence of the fail states. The vertical fail pattern may comprise a single fail state or multi-state fail. The multi-state fail may be a continuous-states fail, discontinuous-states fail, or all-state fail. The multi-level memory defect analysis system and method may additionally enable classification of failed bits or patterns comprising a lateral fail pattern. The lateral fail pattern may be a gradual fail pattern, periodic fail pattern, or random fail pattern.