Multilevel Memory ECC Schemes With Lower Parity Overhead
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Solution Overview
Problem
As technology nodes shrink and the number of bits stored in each cell increases, the raw bit error rate (BER) rises, leading to a need for more parity information bits in nonvolatile memory (NVM) devices, which offsets the gain in storage capacity, especially when using hard-decision ECC solutions like Hamming and BCH codes.
Innovation Solution
The development of advanced error correcting codes (ECC) and calculation systems that select parameters to increase storage capacity while maintaining desired error rates, including the use of concatenated coding schemes with trellis code modulation (TCM) and Reed Solomon (RS) codes, and the calculation of actual bits per cell (ABC) to account for parity costs, allowing for efficient encoding and decoding operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored in each cell is increased, then storage capacity is improved, but the raw bit error rate increases requiring more parity bits which offsets the storage capacity gain
Solution Approach 1:
The patent changes the ECC scheme parameter from traditional hard-decision codes to soft-decision LDPC codes, and optimizes iterative decoding parameters (number of iterations, threshold values) to achieve better error correction efficiency with lower parity overhead, thus maintaining storage capacity while improving reliability
Solution Approach 2:
The patent employs a composite coding approach by combining LDPC codes with specific iterative decoding algorithms and threshold optimization techniques, creating a hybrid error correction system that achieves superior performance compared to traditional single-code approaches
2Reliability
If hard-decision ECC solutions like Hamming and BCH codes are used, then error correction is achieved, but parity overhead increases offsetting storage capacity gains
Solution Approach 1:
The patent transitions from hard-decision ECC parameters to soft-decision LDPC parameters, utilizing probabilistic information and iterative decoding parameters (number of iterations, threshold values) to achieve better error correction with reduced parity bits required
Solution Approach 2:
The patent replaces the mechanical hard-decision threshold comparison with a probabilistic soft-decision system that uses likelihood ratios and iterative message passing, substituting a rigid binary decision mechanism with a more nuanced probabilistic approach
3Reliability
If more parity information bits are added to correct errors, then reliability is improved, but storage capacity is reduced
Solution Approach 1:
The patent optimizes LDPC code parameters including code rate, block length, and iteration count to achieve the desired error rate with minimum parity overhead, and dynamically adjusts decoding thresholds to maximize storage efficiency while maintaining reliability
Data Source
AI summary
Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.