Multilevel Memory ECC with Concatenated Codes for Lower Parity Overhead
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Solution Overview
Problem
The increasing raw bit error rate (BER) due to shrinking technology nodes and higher bits per cell in nonvolatile memory (NVM) devices leads to a corresponding increase in parity information bits, offsetting the gain in storage capacity, especially when using hard-decision ECC solutions like Hamming and BCH codes.
Innovation Solution
The implementation of advanced error correcting code (ECC) schemes and calculation systems that select optimal parameters, such as ECC schemes and bit per cell combinations, to increase storage capacity while maintaining desired error rates, including the use of concatenated codes with trellis code modulation (TCM) and Reed Solomon (RS) codes to reduce parity overhead and improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hard-decision ECC solutions like Hamming and BCH codes are used, then error correction capability is improved, but storage capacity is reduced due to increased parity information bits
Solution Approach 1:
The patent changes the fundamental parameters of error correction by transitioning from hard-decision ECC (Hamming/BCH codes) to soft-decision ECC schemes. This parameter change in the decision mechanism allows for more efficient error correction with reduced parity overhead, thereby improving storage capacity while maintaining reliability
Solution Approach 2:
The patent employs composite coding schemes that combine multiple error correction techniques (concatenated codes combining outer and inner codes, TCM integration) to achieve superior error correction performance with lower parity bit requirements compared to single-code hard-decision approaches
2Quantity of substance
If the number of bits per cell is increased, then storage capacity is improved, but raw bit error rate increases leading to more parity bits needed
Solution Approach 1:
The patent converts the harmful effect of increased raw bit error rate (which naturally occurs with higher bits per cell) into a benefit by using soft-decision ECC that can effectively correct these errors. The soft-decision mechanism leverages analog signal information to correct errors that would be uncorrectable with hard-decision methods, thus enabling high-density storage while maintaining reliability
3Quantity of substance
If technology nodes are shrunk, then device density is improved, but raw bit error rate increases requiring more parity information bits
Solution Approach 1:
The patent applies parameter changes by adopting soft-decision ECC schemes that fundamentally alter how errors are detected and corrected. This change in the error correction parameter allows the system to handle the increased error rates from shrunk technology nodes without proportionally increasing parity bit requirements
Data Source
AI summary
Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.