Multi-Level Memory Encoding for Error-Tolerant Data Storage
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Solution Overview
Problem
Multi-level solid state non-volatile memory systems face increased errors due to reduced signal distance between voltage levels, leading to program and read disturbs, which affect storage density and reliability.
Innovation Solution
Incorporating an analog-to-digital converter to digitize data from multi-level solid state non-volatile memory arrays, allowing for encoding and decoding processes that increase the number of digital levels, thereby enhancing storage density and reliability through improved error correction mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level memory cells are used to increase storage density, then storage density is improved, but error rate increases due to reduced signal distance between voltage levels
Solution Approach 1:
The patent segments the error correction process into multiple stages: first decoding to initial data bits, then second decoding to corrected data bits. This multi-stage segmentation allows progressive error correction, addressing the increased error rates from multi-level cells while preserving storage density benefits.
Solution Approach 2:
The patent applies preliminary error correction by generating and storing check bits alongside data bits before final read operations. This preliminary action prepares the data for subsequent error detection and correction, mitigating the reliability issues of multi-level memory cells in advance.
2Reliability
If more check bits are added for error correction, then reliability is improved, but storage efficiency decreases
Solution Approach 1:
The patent applies partial error correction by using multiple decoding stages rather than attempting to correct all possible errors in a single pass. This partial action approach provides sufficient reliability improvement without requiring excessive check bits, thus maintaining storage efficiency.
Solution Approach 2:
The patent changes the parameters of error correction by using different decoding algorithms in sequence (first decoding then second decoding). This parameter change allows effective error correction with optimized check bit usage, balancing reliability and storage efficiency.
3Reliability
If conventional binary memory is used, then error rate is lower, but storage density is limited
Solution Approach 1:
The patent introduces an intermediary error correction system with multiple decoding stages that mediates between the high error rates of multi-level cells and the data integrity requirements. This intermediary mechanism enables the use of multi-level cells for increased density while maintaining reliability through systematic error correction.
Solution Approach 2:
The patent creates a composite error correction system combining multiple decoding methods and check bit schemes. This composite approach integrates different error correction techniques to handle the specific challenges of multi-level memory, enabling both high density and acceptable reliability.
Data Source
AI summary
A controller for a nonvolatile memory includes an encoder and a decoder. The memory includes memory cells that each store data using more than two levels. The encoder generates first data for storage in first memory cells. For first and second subsets of cells of the first memory cells, the first data is stored at first and second levels, respectively. Measurable values of the first subset of cells are characterized by a first probability density function having a first width. Measurable values of the second subset of cells are characterized by a second probability density function having a second width. The first width is greater than the second width. The encoder generates the first data such that a size of the first subset of cells is less than a size of the second subset of cells. The decoder decodes encoded data from the memory.