Multi-Level Memory Coding with LDPC Interleaving for Signal Distinction
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Solution Overview
Problem
The challenge in multi-level signal memory cells, such as those used in flash memory, is the difficulty in distinguishing between adjacent signal levels due to reduced signal distance, which limits the number of signal levels that can be written into each cell, leading to uncertainty in signal level determination.
Innovation Solution
The implementation of a memory apparatus that uses a low density parity check (LDPC) coder and bit-interleaved code modulation (BICM) to encode and interleave data, combined with pulse amplitude modulation (PAM) and a constellation map based on Gray code, to enhance the reliability of writing and reading multi-level signals, allowing for more levels to be realized in each memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level signal memory cells are used to increase memory capacity, then data density is improved, but signal distance is reduced making adjacent levels difficult to discern
Solution Approach 1:
The signal levels are segmented into distinct groups using LDPC coding and BICM modulation. The interleaver separates adjacent signal levels by distributing them across different positions in the coded sequence, reducing the probability that overlapping distributions will cause misclassification. This segmentation allows the system to maintain 4 distinct signal levels while managing the overlap through structured code design.
Solution Approach 2:
LDPC codes and BICM modulation act as intermediaries between the multi-level signal memory cells and the read-back signal determination. These coding schemes introduce redundancy and structured separation that help the slicer circuit distinguish between adjacent signal levels even when their probability distributions overlap, effectively mediating the measurement process.
2Quantity of substance
If four signal levels are written into each cell, then two bits may be included into each flash memory cell, but uncertainty in signal level determination increases
Solution Approach 1:
LDPC encoding and BICM modulation are applied preliminarily to the data before it is written into the multi-level signal memory cells. This preliminary coding establishes a structured framework that anticipates and compensates for the uncertainty in signal level determination during reading, allowing reliable recovery of the original data despite the overlapping probability distributions of adjacent signal levels.
Solution Approach 2:
The LDPC decoding process incorporates feedback mechanisms that iteratively refine the determination of signal levels. The decoder uses the received signal levels along with the code structure to progressively improve the reliability of bit determination, allowing the system to overcome the uncertainty introduced by writing four signal levels into each cell.
Data Source
AI summary
Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes a low density parity check (LDPC) coder to LDPC code data values to be written into the memory cells and an interleaver adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values. Other embodiments may be described and claimed.