Multi-Level Memory Read Voltage Sharing for Faster Page Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND memory technologies face a trade-off between fast write speed and high reliability, on one hand, and large storage capacity and low cost, on the other, with single-level cells being faster but more expensive and multi-level cells being slower and less reliable.
Innovation Solution
A memory device and system that allows for reading and writing data using shared stages of read voltages across multiple pages, optimizing the read process to improve efficiency and reduce the number of sensing processes, thereby enhancing read speed and reliability while maintaining or increasing storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cells are used to increase storage capacity and reduce cost, then storage capacity increases and cost decreases, but write speed decreases and reliability decreases
Solution Approach 1:
The patent segments the read operation into multiple stages, each stage reading a specific page (first page, second page, third page, fourth page) with different read voltages. This segmentation allows the system to read only the required data pages rather than all pages, effectively increasing read speed while using multi-level cells for high capacity storage.
2Quantity of substance
If multi-level cells are used to increase storage capacity and reduce cost, then storage capacity increases and cost decreases, but reliability decreases
Solution Approach 1:
The patent applies preliminary action by performing read verification at multiple stages during the read operation. The peripheral circuit verifies data integrity at each stage (first stage, second stage, third stage, fourth stage) before completing the read operation, ensuring reliable data retrieval from multi-level cells through proactive error detection.
3Speed
If single-level cells are used to achieve fast write speed and high reliability, then write speed increases and reliability increases, but storage capacity decreases and cost increases
Solution Approach 1:
The patent makes the peripheral circuit universal by enabling it to handle multiple read voltage stages and multiple data pages within a single read operation. The peripheral circuit can selectively read from any combination of the four data pages stored in each memory cell, providing multi-functionality that allows multi-level cells to achieve performance characteristics similar to single-level cells for specific read operations.
4Loss of information
If traditional read operations read all pages, then complete data is retrieved, but read time increases and efficiency decreases
Solution Approach 1:
The patent applies partial action by reading only the necessary data pages (one to four pages) from each memory cell based on the read instruction, rather than reading all pages. The peripheral circuit selectively activates the required number of read voltage stages, reducing read time and energy consumption while still retrieving complete relevant data without unnecessary overhead.
Data Source
AI summary
A memory device includes: a memory cell array including memory cells each storing m data bits, wherein the m data bits correspond to m pages, and each page corresponds to a plurality of stages of read voltages; and a peripheral circuit coupled with the memory cell array and configured to: receive a first read instruction, wherein the first read instruction includes indicating reading of data on n data bits among the m data bits of the memory cells, wherein m and n both are positive integers, and 1<n<m; and in response to the first read instruction, read data of n pages among the m pages, wherein in the reading process, different pages among the n pages share at least one stage of read voltages.