Multilevel Semiconductor Package Shielding for EMI-Sensitive ICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Precision and sensitive ICs in semiconductor packages are adversely affected by electromagnetic interference (EMI) from neighboring components, particularly due to the limited design flexibility of traditional powerpad packages and high inductance of gullwing leads, which hampers effective EMI shielding.
Innovation Solution
A multilevel package substrate, referred to as a routable leadframe, is used to create an EMI-shielded semiconductor package, featuring a top and bottom metal shield connected by metal pillars, resembling a Faraday cage, which embeds the IC within a grounded metal layer structure to reduce parasitics and inductance, thereby enhancing EMI shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional powerpad package (PWP) with gullwing leads is used, then the IC can be packaged with conventional design, but EMI shielding effectiveness is poor due to limited design flexibility and high inductance of gullwing leads
Solution Approach 1:
The patent transitions from a conventional two-dimensional package layout to a three-dimensional multilevel substrate structure with multiple metal shielding layers stacked vertically. The first and second metal shielding layers are positioned at different heights above and below the IC, creating a volumetric Faraday cage that provides superior EMI protection while maintaining compact footprint.
Solution Approach 2:
The IC is embedded within a nested structure of multiple shielding layers. The first metal shielding layer is positioned above the IC, the second metal shielding layer below the IC, and both are connected through vertical conductive vias, creating a nested Faraday cage configuration that encapsulates the IC for comprehensive EMI protection.
2Ease of manufacture
If gullwing leads with wirebonds are used to connect IC bond pads, then conventional connection methods can be used, but inductance is high causing increased ringing that reduces EMI shielding effect
Solution Approach 1:
The patent extracts and eliminates the gullwing leads and wirebond connections from the package design. Instead, the IC bond pads are directly connected to the multilevel substrate's internal metal traces and vias, removing the high-inductance external connection elements that caused ringing and compromised EMI shielding effectiveness.
Solution Approach 2:
The mechanical wirebond connection system is replaced with an integrated electrical connection system using conductive vias and planar traces on the multilevel substrate. This substitution eliminates the inductive effects of wirebonds while maintaining electrical connectivity, thereby reducing ringing and improving overall signal integrity and EMI shielding.
3Area of stationary object
If precision IC is placed in proximity to EMI emitting components on the same PCB, then board space utilization is efficient, but performance of precision IC degrades due to EMI
Solution Approach 1:
The patent applies preliminary anti-action by pre-establishing a Faraday cage structure around the precision IC before the IC is exposed to EMI from neighboring components. The multiple grounded metal shielding layers are positioned to intercept and redirect EMI fields away from the IC, proactively preventing interference rather than attempting to mitigate it after the fact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces EMI impact on precision and sensitive ICs, improving their performance by minimizing ringing and enhancing shielding effectiveness, as demonstrated by a three-fold reduction in electric field strength compared to conventional packages.
Implementation Method 1
The top and bottom EMI shields together with the metal pillars positioned beyond the area of the IC that can define an area beyond the area of the IC referred to herein as a ring around the IC, where the EMI shields together with the metal pillars collectively resemble a Faraday cage for the IC die
Data Source
AI summary
A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.