Multilevel Page Table Structure for Memory Management
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Solution Overview
Problem
Existing memory management systems face inefficiencies due to the use of separate page tables for each process and the lack of matching page table levels with supported page sizes, leading to complex logic, slow operation, and suboptimal processor and memory resource usage.
Innovation Solution
Implementing a multilevel page table structure where the depth and order of sub-arrays correspond to the supported page sizes, allowing a single data structure to reference virtual memory pages, reducing page table size and cache misses, and enhancing memory usage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate data structures are used to reference each page in a page table, then individual page tracking is improved, but memory efficiency deteriorates
Solution Approach 1:
The patent combines multiple separate data structures into a unified page table structure. Instead of maintaining separate data structures for each page, the invention creates a single integrated page table that manages all pages efficiently, reducing overall memory consumption while maintaining the ability to track individual pages through standardized entry formats.
Solution Approach 2:
The page table structure is designed to be universal and multi-functional, serving both small and large pages through a single data structure. The standardized page table entries can represent different page sizes without requiring separate specialized structures, thereby improving memory efficiency while maintaining precise tracking capabilities across various page types.
2Quantity of substance
If page tables are paged to secondary memory when main memory is low, then memory capacity is improved, but operation speed deteriorates
Solution Approach 1:
The patent implements preliminary action by pre-organizing page tables in an optimized structure that anticipates future memory management needs. The page table is designed with a hierarchical structure that allows portions to be kept in main memory based on usage patterns, reducing the need to page to secondary memory and maintaining operation speed while managing memory capacity effectively.
3Adaptability or versatility
If arbitrary page sizes are used in multilevel page tables, then flexibility is improved, but processor and memory resource usage deteriorates
Solution Approach 1:
The patent applies local quality by allowing different regions of the virtual address space to use different page sizes based on local requirements. Rather than using arbitrary page sizes throughout, the system selectively applies appropriate page sizes to specific address ranges, optimizing processor and memory resource usage while maintaining the flexibility to adapt to different access patterns and memory management needs in different locations.
Data Source
AI summary
Systems, methods, and devices are provided for memory management. One method embodiment includes providing an operating system capable of supporting variable page sizes. The method includes providing a virtual memory address, translating the virtual memory address to a virtual memory page, and mapping the virtual memory page to a physical memory page by using a multilevel page table whose depth and/or order corresponds to page sizes that are supported by an operating system and/or hardware.