Multilevel Photoresist Patterning for Sub-Resolution Semiconductor Features
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Solution Overview
Problem
Current semiconductor manufacturing methods face limitations in increasing density, yield, throughput, and reducing costs due to minimum dimension constraints in lithography systems, particularly in achieving smaller feature sizes and pitches in semiconductor devices.
Innovation Solution
A method involving the formation of a multilevel photoresist structure with a protection layer over a target material, allowing for a single etch step to create multilevel recesses, which enables double patterning capability without an additional etch step, thereby improving manufacturing efficiency and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography systems are used to transfer patterns to the wafer, then manufacturing process is simple, but feature size and pitch are limited by the resolution limit of the lithography system
Solution Approach 1:
The patent divides a single complex patterning operation into multiple sequential exposure and development steps. First, a preliminary pattern is formed and developed, then a second exposure is performed to create the final pattern. This segmentation allows achieving sub-resolution features while maintaining process control and using existing lithography equipment.
Solution Approach 2:
The patent performs a preliminary exposure to create a preliminary pattern that serves as a foundation for the final pattern. This preliminary pattern is developed and then used as a mask or template for the second exposure, enabling the formation of features smaller than the lithography system's native resolution limit.
2Manufacturing precision
If double exposure technique is used to extend lithography system below its resolution limit, then feature size is reduced, but production throughput is impacted
Solution Approach 1:
The patent merges two exposure operations into a single wafer processing cycle by performing the second exposure while the wafer remains on the lithography system without removing it for intermediate processing steps. This merging approach maintains the benefits of double patterning for achieving sub-resolution features while minimizing the impact on production throughput.
Solution Approach 2:
The patent maintains continuous processing by performing sequential exposures and developments without removing the wafer from the lithography system or introducing idle time between steps. The second exposure is performed immediately after the first, and developments are conducted in continuous sequence, ensuring uninterrupted useful action throughout the patterning process.
3Manufacturing precision
If more semiconductor devices are packed into smaller physical space to increase density, then integration is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent transitions from conventional single-layer patterning to a multi-dimensional approach by performing multiple exposures on the same wafer surface at different pattern configurations. This dimensional change in the patterning process enables achieving higher density and smaller features without requiring new lithography equipment or fundamentally changing the manufacturing architecture.
Solution Approach 2:
The patent changes the exposure parameters between the first and second exposures, including exposure dose, pattern configuration, and development conditions. These parameter changes enable the formation of different pattern features in sequence, achieving high density and small feature sizes while using the same lithography system and materials, thereby controlling manufacturing cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances manufacturing throughput, achieves feature sizes and pitches smaller than the lithography system's capability, and supports cost reduction by reusing existing equipment, resulting in increased integration and density with improved yield.
Implementation Method 1
forming a multilevel photoresist structure
Data Source
AI summary
A method for forming a semiconductor device is provided including processing a wafer having a target material, forming a multilevel photoresist structure having a protection layer over the target material, and forming a multilevel recess in the target material with the multilevel photoresist structure.