Multilevel Power Converter Using Nested Cells and Anti-Series Semiconductors
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Solution Overview
Problem
Existing multilevel electronic power converters are hindered by large size, high cost, and complexity due to excessive use of semiconductors and capacitors, which limits the number of attainable voltage levels and increases conduction losses.
Innovation Solution
A multilevel electronic DC/AC or AC/DC power converter design featuring a reduced number of high-current capacitors and semiconductors, utilizing intermediate semiconductors connected in anti-series and high-frequency low-current capacitors to enable efficient operation with n output voltage levels, thereby reducing the size and cost while maintaining high current capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of voltage levels is increased to improve power capacity and current quality, then the power and current quality are improved, but the size and cost of the converter increase
Solution Approach 1:
The converter is divided into multiple independent cells, each contributing a specific voltage level. By segmenting the overall converter into modular cells that can be selectively activated, the system achieves high voltage levels without requiring all components to be present simultaneously, thus reducing the overall size and cost while maintaining high power capacity.
Solution Approach 2:
The patent implements a nested structure where cells are arranged in series-parallel configurations, with inner cells nested within outer cell structures. This nesting allows multiple voltage levels to be achieved within a compact footprint, as smaller cell units are integrated within larger structural frameworks, reducing the total volume required for high-voltage operation.
2Reliability
If the number of voltage levels is increased to improve current quality, then the harmonic content is reduced, but the device complexity increases
Solution Approach 1:
Each cell in the converter is designed with universal functionality, capable of operating in multiple modes (active, passive, blocking) and serving multiple purposes simultaneously. This multi-functionality reduces the need for specialized components for each voltage level, thereby simplifying the overall device structure while maintaining high current quality and low harmonic content.
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting the switching states and connection configurations of cells based on operating conditions. By changing parameters such as cell activation patterns, switching frequencies, and connection topologies, the converter achieves optimal current quality across different power levels without requiring complex dedicated circuits for each scenario.
3Quantity of substance
If additional semiconductors are added to reduce capacitor requirements, then the number of capacitors is reduced, but the cost and size increase
Solution Approach 1:
The patent merges the functions of multiple capacitors into shared energy storage elements that serve multiple cells simultaneously. By combining capacitor functions across cell boundaries and using common DC bus capacitors for multiple voltage levels, the total capacitor count is reduced while the increased semiconductor count is offset by the elimination of redundant capacitor structures.
Data Source
AI summary
The invention is a multilevel electronic DC/AC or AC/DC power converter for n output voltage levels with a positive branch (POS) with a positive DC voltage terminal (2), a negative branch (NEG) with a negative DC voltage terminal (1), and an AC voltage terminal (3) connected to the positive branch (POS) and to the negative branch (NEG), DC bus capacitors (4) interconnected between positive (2) and negative (1) DC voltage terminals and an intermediate DC voltage terminal (5) connected between the two DC bus capacitors (4); a plurality of first external controlled semiconductors (6) and second external controlled semiconductors (7) and, at least, one high-current DC capacitor (11), at least two high-frequency and low-current capacitors (12) and one intermediate controlled semiconductor (8) connected between the intermediate DC voltage terminal (5) and an intermediate terminal (10) of an internal branch (INT) connected in parallel with each high-current DC capacitor (11).