Multilevel PWM Switching for CMV Reduction and Capacitor Balancing
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Solution Overview
Problem
Conventional multilevel power converters for hybrid-electric aircraft propulsion systems face challenges in reducing common mode emissions and associated electromagnetic interference, which often require additional hardware to balance DC link capacitor voltages, increasing weight and cost.
Innovation Solution
The implementation of Pulse Width Modulated (PWM) switching schemes that generate a PWM pulse pattern based on a reduced Common Mode Voltage (CMV) scheme, adjusting pulses to balance voltages across DC link capacitors without additional hardware, thereby reducing CMV and electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional PWM switching schemes are used to reduce common mode emissions, then electromagnetic interference is reduced, but additional hardware is required to balance DC link capacitor voltages, increasing weight and device complexity
Solution Approach 1:
The PWM switching scheme is designed to automatically balance the DC link capacitor voltages through intelligent pulse generation and adjustment. The controller monitors the capacitor voltages and dynamically adjusts the PWM pulses to transfer energy between capacitors, enabling the system to self-regulate without external balancing hardware.
Solution Approach 2:
The invention changes the timing, width, and sequence of PWM pulses to achieve both common mode emission reduction and capacitor voltage balancing. By dynamically adjusting pulse parameters based on capacitor voltage states, the system achieves dual objectives without additional hardware components.
2Stability of the object's composition
If additional hardware is added to balance DC link capacitor voltages, then voltage balancing is achieved, but weight and device complexity increase
Solution Approach 1:
The PWM switching scheme is designed to automatically balance the DC link capacitor voltages through intelligent pulse generation and adjustment. The controller monitors the capacitor voltages and dynamically adjusts the PWM pulses to transfer energy between capacitors, enabling the system to self-regulate without external balancing hardware.
Solution Approach 2:
The invention extracts the voltage balancing function from separate hardware components and integrates it into the control logic of the PWM switching scheme. By removing the need for external balancing circuits, the system achieves voltage balancing while reducing overall weight and complexity.
3Stability of the object's composition
If additional hardware is added to balance DC link capacitor voltages, then voltage balancing is achieved, but system size and filter requirements increase
Solution Approach 1:
The PWM switching scheme performs multiple functions simultaneously: it controls the power conversion, reduces common mode emissions, and balances DC link capacitor voltages. This multi-functionality eliminates the need for separate balancing hardware, reducing overall system volume and filter requirements.
Solution Approach 2:
The invention merges the voltage balancing function with the primary power conversion function by integrating it into the PWM control logic. By combining these functions into a single control mechanism, the system reduces the number of separate components and overall system volume.
4Power
If conventional PWM schemes are used, then power conversion is achieved, but common mode voltage pulses are generated, causing electromagnetic interference
Solution Approach 1:
The invention converts the harmful common mode voltage pulses into beneficial voltage balancing actions. By strategically injecting common mode pulses during specific switching intervals, the system transfers energy between DC link capacitors to balance their voltages, turning a previously harmful effect into a useful function.
Solution Approach 2:
The PWM switching scheme employs periodic pulse patterns with specific timing and sequencing to minimize common mode emissions. By using complementary switching patterns across multiple legs of the converter, the system periodically cancels out common mode voltage pulses while maintaining effective power conversion.
Data Source
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AI summary
A multilevel power converter (200) includes a plurality of switches (242), a first DC link capacitor (C1), a second DC link capacitor (C2), and one or more processors (610A) configured to: generate, for a duty cycle of the multilevel power converter (200), a pulse width modulated pulse pattern (226) in accordance with a reduced common mode voltage scheme; modify the pulse width modulated pulse pattern (226) to render a modified pulse pattern (236); and cause the plurality of switches (242) to implement the duty cycle based at least in part on the modified pulse pattern (236) to render a common mode voltage pulse (CMVP1) to balance voltages at the first DC link capacitor (C1) and the second DC link capacitor (C2).