Multi-Level Memory Read-Voltage Calibration for Lower Read Errors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory devices with multi-bit per memory cell storage architecture face narrower read margins, making them vulnerable to noise, program/read disturbances, coupling issues, and charge loss, leading to increased read errors.
Innovation Solution
A method to determine optimal read voltages by performing a first read operation with a single read level, comparing expected and actual bit counts, and adjusting read voltages based on differences to find the optimal read voltage, reducing read errors and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit per memory cell storage architecture is used, then storage capacity is improved, but read margins become narrower and read errors increase
Solution Approach 1:
The patent performs preliminary read operations at different read levels before the final read operation. By conducting read operations at multiple read levels (first read level, second read level, third read level) and comparing bit counts, the system preliminarily determines the actual data state and adjusts subsequent read operations accordingly, thereby compensating for narrow read margins in multi-bit storage architecture
Solution Approach 2:
The patent implements a feedback mechanism where bit counts from preliminary read operations are compared against expected bit count ranges. Based on this comparison feedback, the system determines whether to perform additional read operations at different read levels or to proceed with error correction, dynamically adjusting the read process to maintain reliability in multi-bit storage
2Measurement precision
If multiple read operations are performed to determine optimal read voltage, then read accuracy is improved, but operation time increases
Solution Approach 1:
The patent performs read operations at a limited number of specific read levels (first, second, and third read levels) rather than exhaustively searching all possible read voltages. By selecting key read levels strategically and comparing bit counts at these levels, the system achieves sufficient read accuracy without the time cost of comprehensive voltage scanning
Solution Approach 2:
The patent segments the read operation into distinct stages: preliminary read operations at different read levels, bit count comparison and analysis, and final read execution. This segmentation allows the system to efficiently determine optimal read parameters through structured multi-level reads rather than unoptimized sequential trials, balancing accuracy and time
Data Source
AI summary
A method of operating a memory system includes performing a first read operation with a first read voltage of a first single read level, determining an actual pattern of bit count under the first read voltage of the first single read level, and in response to that a difference between an expected pattern of bit count and the actual pattern of bit count under the first read voltage of the first single read level is equal to or lower than a first threshold, determining that the first read voltage is a first optimal read voltage. The first single read level of a first page is under a multi-level architecture.