Multi-Level Signal Receiver with Split Pre-Amplifier Linearity Control
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Solution Overview
Problem
Semiconductor memory devices face challenges in minimizing non-linearity and reducing power consumption and size when receiving multi-level signals, particularly due to linearity degradation caused by decreased headroom margin in multi-level signaling.
Innovation Solution
A receiver is designed with a pre-amplifier circuit comprising multiple circuits with different structures, optimized for various reference levels, which reduces linearity degradation and power consumption, and includes a slicer and decoder circuit to generate multi-bit data from multi-level signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-level signaling is used to increase data transmission efficiency, then productivity is improved, but non-linearity and linearity degradation occur due to decreased headroom margin
Solution Approach 1:
The patent applies local quality by configuring different circuits within the pre-amplifier with different structures optimized for specific reference levels. Specifically, first circuits are configured for first reference levels and second circuits are configured for second reference levels, allowing each circuit to maintain optimal linearity for its designated voltage range while collectively handling the full multi-level signal spectrum
Solution Approach 2:
The pre-amplifier is segmented into multiple independent circuits, each handling specific portions of the multi-level signal based on reference level comparisons. This segmentation allows the system to process different voltage levels through specialized circuit paths, reducing overall non-linearity while maintaining high data transmission efficiency
2Device complexity
If traditional pre-amplifier structures are used to maintain simplicity, then device complexity is reduced, but power consumption increases
Solution Approach 1:
Different circuits within the pre-amplifier are designed with structures optimized for their specific operational ranges and reference levels. This localized optimization allows each circuit to operate more efficiently in its designated range, reducing overall power consumption while maintaining manageable device complexity through systematic design
3Device complexity
If traditional pre-amplifier structures are used to maintain simplicity, then device complexity is reduced, but size increases
Solution Approach 1:
By configuring circuits with different structures for different reference levels, the patent achieves compact integration where each circuit is optimized for its specific function. This approach reduces overall receiver size compared to traditional uniform structures, as each circuit can be minimized for its particular operational requirements rather than being oversized to handle all possible signal levels
Data Source
AI summary
A receiver that receives a multi-level signal includes a pre-amplifier circuit, a slicer circuit and a decoder circuit. The pre-amplifier circuit generates a plurality of intermediate data signals based on an input data signal and a plurality of reference voltages. The slicer circuit generates a plurality of decision signals based on the plurality of intermediate data signals and a clock signal. The decoder circuit generates output data based on the plurality of decision signals. The pre-amplifier circuit includes a first circuit and a second circuit. The first circuit generates one of the plurality of intermediate data signals based on the input data signal and one of the plurality of reference voltages, and has a first structure. The second circuit generates another one of the plurality of intermediate data signals based on the input data signal and another one of the plurality of reference voltages, and has a second structure different from the first structure.