Multilevel Region Coherence Protocol for Clustered Shared-Memory Systems
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Solution Overview
Problem
Existing two-level cache coherence protocols in clustered shared-memory multiprocessor systems are inefficient as they consume more SMP node bandwidth and power due to delayed memory requests and lack of spatial locality optimization, and prior proposals like 'pseudo invalid' states and Region Coherence Arrays are suboptimal for clustered systems.
Innovation Solution
A multilevel region coherence protocol that uses one bit per interconnect hierarchy level to indicate the presence of cached data, allowing targeted memory requests and reducing unnecessary broadcasts, thereby optimizing bandwidth, power, and latency by identifying the appropriate levels to send requests and implementing dynamic self-invalidation without discarding external status.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If memory requests are first broadcast to local SMP node before other SMP nodes, then global bandwidth requirements are reduced, but SMP node bandwidth and power consumption increase due to delayed requests
Solution Approach 1:
The patent segments the interconnect hierarchy into multiple levels (e.g., L1 cache, L2 cache, L3 cache, system memory) and introduces region coherence state bits at each level to track data presence. This segmentation allows requests to be targeted at specific hierarchy levels based on where data is likely to be found, avoiding unnecessary broadcasts to all SMP nodes while reducing local node bandwidth consumption.
Solution Approach 2:
The patent performs preliminary action by setting region coherence state bits in advance to indicate which hierarchy levels are likely to contain cached data. When a memory request arrives, the system checks these pre-set state bits to determine the appropriate target level, eliminating the need to broadcast to all levels first. This preliminary tracking of data location information allows direct targeting of requests, reducing both global and local bandwidth consumption.
2Productivity
If pseudo invalid states are used to predict cached data location, then subsequent requests are optimized, but initial requests are delayed and spatial locality beyond cache line is not exploited
Solution Approach 1:
The patent extends the coherence tracking from individual cache lines to entire regions (spatial dimension) and from temporal reuse to hierarchical level tracking (adding a new dimension). By tracking region coherence state at multiple hierarchy levels simultaneously, the system can optimize both initial and subsequent requests by directing them to the appropriate hierarchy level based on region-wide data presence information, rather than treating each cache line in isolation.
Solution Approach 2:
The patent introduces region coherence state bits as intermediary indicators between the cache hierarchy and the request routing mechanism. These state bits serve as mediators that provide information about data presence at different hierarchy levels, enabling the system to make informed routing decisions for both initial and subsequent requests without requiring full broadcasts, thus reducing latency while maintaining optimization benefits.
3Loss of energy
If region coherence tracking is implemented, then bandwidth is optimized, but protocol complexity increases with additional hierarchy levels
Solution Approach 1:
The patent changes the parameter representation by using a single region coherence state bit per hierarchy level instead of maintaining separate tracking information for each cache line or processor. This parameter change simplifies the protocol complexity while maintaining the ability to track data presence across multiple hierarchy levels, as the state bits can be updated en masse based on cache fill and evict operations rather than requiring individual line tracking.
Solution Approach 2:
The region coherence state bits serve multiple functions: they track data presence at different hierarchy levels, guide request routing decisions, and enable dynamic self-invalidation. This multi-functionality reduces the need for separate protocol mechanisms for each function, thereby reducing overall protocol complexity while achieving bandwidth optimization across the hierarchical interconnect.
4Ease of operation
If dynamic self-invalidation is implemented, then exclusive access is facilitated, but useful external status information is discarded
Solution Approach 1:
The patent implements a refined dynamic self-invalidation mechanism that selectively invalidates region coherence state information only when necessary (when another processor obtains exclusive access), while recovering and preserving the external status information by updating the state bits to reflect the new exclusive owner. This allows the system to facilitate exclusive access while maintaining useful information about data location and ownership for future request routing, preventing information loss.
Data Source
AI summary
A system and method of a region coherence protocol for use in Region Coherence Arrays (RCAs) deployed in clustered shared-memory multiprocessor systems which optimize cache-to-cache transfers by allowing broadcast memory requests to be provided to only a portion of a clustered shared-memory multiprocessor system. Interconnect hierarchy levels can be devised for logical groups of processors, processors on the same chip, processors on chips aggregated into a multichip module, multichip modules on the same printed circuit board, and for processors on other printed circuit boards or in other cabinets. The present region coherence protocol includes, for example, one bit per level of interconnect hierarchy, such that the one bit has a value of “1” to indicate that there may be processors caching copies of lines from the region at that level of the interconnect hierarchy, and the one bit has a value of “0” to indicate that there are no cached copies of any lines from the region at that respective level of the interconnect hierarchy.