Multi-Level Routing Matrices for Reconfigurable Pattern Processors
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Solution Overview
Problem
Conventional pattern-recognition processors face performance bottlenecks due to the increasing number of patterns to be identified, as they rely on physical wires and finite state machines that are not configurable or capable of meeting the required speed and configurability for efficient data stream processing.
Innovation Solution
A multi-level hierarchical routing matrix architecture is introduced, allowing for parallel processing of multiple search criteria and dynamic reconfiguration of connections between feature cells, enabling efficient evaluation of large volumes of data without significant performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional physical wire connections and finite state machines are used in pattern-recognition processors, then the processor can be manufactured with standard silicon technology, but the processor cannot meet the required speed and configurability for efficient data stream processing
Solution Approach 1:
The routing matrix is divided into multiple hierarchical levels (first level, second level, third level) with each level handling specific routing functions. This segmentation allows the complex routing task to be distributed across multiple simpler sub-routers, improving both configurability and managing complexity.
Solution Approach 2:
The patent introduces a multi-level hierarchical structure that adds vertical dimensionality to the routing architecture. Instead of a flat single-level routing matrix, the solution stacks multiple routing levels that can be selectively activated, transforming the routing problem from a two-dimensional plane to a three-dimensional hierarchical space.
2Productivity
If multiple search criteria are evaluated sequentially one at a time, then the processor implementation is simple, but the processing speed decreases and creates a computing bottleneck
Solution Approach 1:
Multiple search criteria evaluations are merged into a single parallel processing operation. The routing matrix enables simultaneous activation of multiple feature cell groups, each evaluating different search criteria on the same data stream, combining what would traditionally be sequential operations into one parallel execution cycle.
Solution Approach 2:
The processor architecture dynamically reconfigures the routing matrix to activate different combinations of feature cell groups based on the specific search criteria being evaluated. This dynamic adaptation allows the same hardware to efficiently handle varying numbers and types of patterns without requiring dedicated hardware for each search criterion.
3Adaptability or versatility
If the number of patterns to be identified increases, then the recognition capability improves, but the delay before the system is ready to search the next portion of the data stream increases
Solution Approach 1:
The feature cells are organized into multiple groups that can be independently activated. When searching for multiple patterns, only the relevant feature cell groups need to be activated rather than processing all possible patterns, segmenting the computational workload to reduce delay while maintaining comprehensive pattern recognition capability.
Solution Approach 2:
The routing matrix serves multiple functions: it routes data to active feature cell groups, enables parallel evaluation of multiple search criteria, and supports dynamic reconfiguration for different pattern sets. This multi-functionality allows the same hardware structure to handle increasing pattern recognition requirements without proportionally increasing search delay.
Data Source
AI summary
Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.