Multilevel Semiconductor Image Sensor Stacking
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Solution Overview
Problem
Current image sensors face challenges such as limited light sensitivity due to the integration of photodetectors and sensing circuitry on the same chip, alignment issues in stacking technologies like TSV, and the sequential shifting of image information in CCD sensors, which affects speed and cell density, and the trade-off in dynamic range between bright and dark areas in HDR imaging.
Innovation Solution
The use of layer transfer technology to monolithically stack photodetectors and read-out circuits, allowing for parallel data collection and the integration of image sensors with distinct light-sensitive areas and read-out circuits, and the implementation of algorithms for reconstructing objects and gesture recognition systems using dual image sensor arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If photodetectors and sensing circuitry are integrated on the same chip, then device complexity is reduced, but light sensitivity deteriorates due to area consumed by sensing circuits
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking, placing photodetectors and sensing circuitry on separate layers vertically connected via TSVs. This dimensional change allows both components to occupy different spatial planes, eliminating the area trade-off while maintaining integration benefits.
Solution Approach 2:
The integrated sensor is segmented into distinct functional layers: photodetector layer for light detection and sensing circuitry layer for signal processing. This segmentation allows each component to be optimized independently while maintaining compact integration through vertical stacking.
2Illumination intensity
If TSV stacking technology is used to separate photodetectors and sensing circuitry, then light sensitivity is improved, but manufacturing precision deteriorates due to alignment issues
Solution Approach 1:
Alignment marks are pre-formed on both the photodetector layer and sensing circuitry layer before the bonding process. These preliminary markers enable precise alignment to be achieved during stacking, compensating for the inherent alignment challenges of TSV technology.
Solution Approach 2:
Alignment marks serve as intermediary reference elements that facilitate the bonding process. These markers act as mediators between the two layers, enabling accurate positioning and reducing alignment errors during the stacking operation.
3Device complexity
If readout circuits are placed at the edge of CCD sensors, then device complexity is reduced, but speed deteriorates due to sequential shifting of image information
Solution Approach 1:
The patent moves the readout circuits from the lateral edge position to a vertical stacking configuration directly beneath the photodetector array. This dimensional repositioning enables parallel readout of multiple pixels simultaneously, eliminating the sequential shifting bottleneck while simplifying the overall circuit architecture.
Data Source
AI summary
An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of first image sensors; and a third level overlaying the second level, where the third level includes a plurality of second image sensors, where the second level is bonded to the first level, where the bonded includes an oxide to oxide bond; and an isolation layer disposed between the second mono-crystal layer and the third level.