Multilevel Semiconductor Device With Waveguide Oxide Layer
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Solution Overview
Problem
Current methods for constructing RGB LEDs, image sensors, displays, and solar cells face challenges such as high costs, inefficiencies, and thermal expansion coefficient mismatches, which hinder the development of more efficient and cost-effective devices.
Innovation Solution
The use of smart layer transfer techniques, including ion-cut, porous silicon approaches, and oxide-to-oxide bonding, allows for the construction of multi-level semiconductor devices with integrated circuits and optical waveguides, enabling the creation of efficient RGB LEDs, image sensors, and solar cells at lower temperatures and reduced costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding methods are used to construct multi-level semiconductor devices, then device functionality is achieved, but thermal expansion coefficient mismatches cause stress and reliability issues
Solution Approach 1:
The patent introduces an intermediate oxide layer between dissimilar semiconductor substrates (e.g., silicon and sapphire) that serves as a stress-buffering mediator. This oxide layer has thermal expansion properties intermediate between the two substrates, reducing thermal stress during temperature cycling and improving device reliability without compromising bonding functionality.
2Strength
If high temperature processing is used to achieve strong bonding, then bond strength is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent modifies the bonding interface parameters by introducing oxide layers with specific thermal and mechanical properties that enable strong bonding at reduced temperatures. This parameter change allows achieving adequate bond strength (improving feature) while avoiding the high temperature processing that creates complexity in manufacturing (worsening feature).
3Manufacturing precision
If multiple separate processes are used for layer transfer and bonding, then manufacturing precision is maintained, but productivity decreases
Solution Approach 1:
The patent combines multiple separate manufacturing steps (layer transfer, oxide deposition, and bonding) into an integrated monolithic 3D process flow. By merging these processes and using smart-cut technology to pre-form oxide layers on substrates before bonding, the patent maintains manufacturing precision while significantly improving productivity through reduced process cycles.
4Ease of manufacture
If conventional LED construction methods are used, then device functionality is achieved, but cost and efficiency are suboptimal
Solution Approach 1:
The patent creates a universal monolithic 3D platform that can simultaneously fabricate multiple device types (LEDs, image sensors, solar cells) using the same base process technology. This multi-functionality allows optimization of manufacturing costs through platform standardization while improving device efficiency through integrated design, resolving the contradiction between ease of manufacture and productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of more efficient and cost-effective RGB LEDs, image sensors, and solar cells by reducing thermal processing temperatures and improving the bonding quality, thus overcoming the limitations of existing technologies.
Implementation Method 1
an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds
Data Source
AI summary
A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including an electromagnetic waveguide, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.


