Multilevel Shared Database for FPGA Routing Memory Compression
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Solution Overview
Problem
As FPGA sizes increase, the number of wires associated with routing grows, leading to a significant increase in memory consumption for storing routing graphs, making computer systems used to implement routers more costly.
Innovation Solution
A multilevel shared database for routing is introduced, where routing edges are defined by tile templates associated with wire length segmentations, and tile templates are shared among tiles, with pointers pointing to wire templates, reducing memory footprint by decomposing wire representations into position and wire information to determine successor wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA chip size increases, then routing capabilities and functionality improve, but memory consumption for storing routing graphs increases significantly
Solution Approach 1:
The routing graph is segmented into multiple levels: level 0 contains unique wire templates, level 1 contains tile templates that reference wire templates, and level 2 contains individual tile references. This hierarchical segmentation allows shared routing patterns to be stored once at higher levels while individual tiles reference them, dramatically reducing memory consumption for large FPGAs
Solution Approach 2:
Tile templates serve multiple functions: they define routing edges for multiple wires, reference shared wire templates, and can be reused across different tiles. A single tile template can represent the routing structure for many identical or similar tiles in the FPGA, reducing redundant storage
2Quantity of substance
If routing graph memory increases, then more wires can be accommodated, but computer system cost increases
Solution Approach 1:
Instead of storing complete routing graph data for each wire, the system creates templates (wire templates and tile templates) that can be copied and referenced repeatedly. Each tile references templates rather than storing duplicate routing information, reducing memory requirements and thus computer system costs while maintaining the ability to accommodate large numbers of wires
Data Source
AI summary
A multilevel shared database for routing for an integrated circuit is described. An aspect relates generally to a database comprising routing edges defined by tile templates. The routing edges are associated with a plurality of wire length segmentations. The tile templates are associated with tiles of an integrated circuit. The tiles are repeated circuit blocks forming an array. A portion of the tile templates are shared among a portion of the tiles such that the tile templates are less in number than the tiles. The tile templates are associated with pointers for pointing to wire templates.