Multilevel Signal-Line Encoding for Higher Bus Throughput
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Solution Overview
Problem
Current computing systems face challenges in increasing data transfer rates over interface buses without escalating energy consumption, as faster clock speeds outpace DRAM transistor switching capabilities, leading to increased complexity and cost with special purpose, multi-level bus architectures.
Innovation Solution
Implementing a multilevel communication architecture that encodes multiple bitstreams into fewer multilevel signals, using pulse-amplitude modulation and data bus inversion techniques to drive multiple voltage levels on existing signal lines, reducing the need for additional I/O pins and maintaining energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If special purpose, multi-level bus architectures are implemented to increase data transfer rates, then throughput is improved, but device complexity and cost increase
Solution Approach 1:
The patent applies universality by enabling existing binary signal lines to perform multi-level communication functions through encoding schemes. The encoder converts multiple bitstreams into a reduced set of signal lines that can represent more than two states, allowing the same physical infrastructure to achieve higher throughput without requiring specialized multi-level bus hardware. This resolves the contradiction by making the existing binary architecture multi-functional rather than creating new special-purpose architectures.
Solution Approach 2:
The patent changes the parameter representation by using encoding schemes that map multiple bit values onto fewer signal lines through voltage level modulation. The encoder transforms binary data into multi-level signals that can be transmitted over existing binary-compatible interfaces, effectively changing how data is parameterized without changing the physical bus architecture. This allows increased data transfer rates while maintaining compatibility with existing binary infrastructure.
2Productivity
If additional I/O pins are added to increase data transfer capacity, then throughput is improved, but device complexity and cost increase
Solution Approach 1:
The patent applies merging by combining multiple bitstreams into a reduced set of signal lines through encoding. The encoder consolidates data from multiple sources into fewer output channels, allowing multiple data streams to share the same physical I/O pins. This resolves the contradiction by enabling increased data transfer capacity through logical combination rather than physical multiplication of I/O pins.
Solution Approach 2:
The patent introduces another dimension by adding voltage level modulation to the traditional binary signal space. Instead of only using 0 and 1 states, the system utilizes multiple voltage levels to encode additional information on the same signal lines. This dimensional expansion allows more data to be transmitted through the same number of I/O pins by exploiting the voltage amplitude dimension rather than requiring additional pins.
3Productivity
If clock speeds are increased to match faster data transition times, then data transfer rate is improved, but energy consumption increases
Solution Approach 1:
The patent applies periodic action by using structured encoding schemes that process data in defined time intervals and patterns. The encoder and decoder use systematic, periodic transformations of data that can be executed efficiently at lower clock speeds compared to raw high-speed transmission. This allows optimized energy consumption by using rhythmic, predictable processing patterns rather than continuous high-speed switching.
Solution Approach 2:
The patent changes the temporal parameters of data transmission by using encoding schemes that pack more information into each signal transition. By representing multiple bits per signal line transition through voltage level encoding, the system reduces the total number of transitions required to transmit a given amount of data, thereby lowering the cumulative energy consumption even at moderate clock speeds.
Data Source
AI summary
Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers. A driver of the individual drivers is configured to drive more than two voltages.