Multilevel Signaling Buffer Die Channel Distortion Compensation
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Solution Overview
Problem
High-bandwidth memory systems using multilevel signaling face challenges with signal distortion and mismatch between channels due to narrow voltage level intervals, leading to poor signal integrity and increased manufacturing costs associated with the use of silicon interposers.
Innovation Solution
A high-bandwidth memory system that integrates a digital signal processing function on a buffer die, compensating for channel distortion and mismatch without the need for an interposer, utilizing multilevel signaling through channels provided by a package substrate, and including analog-to-digital converters, compensation circuits, and decoders to convert and process multilevel signals into binary signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multilevel signaling is used to increase data rate, then transmission speed is improved, but signal distortion increases due to narrow voltage level intervals
Solution Approach 1:
An interposer is introduced as an intermediary component between the HBM stack and the logic chip to provide dedicated signal paths and impedance control, thereby maintaining signal integrity while enabling multilevel signaling for high data rates
Solution Approach 2:
The system transitions from binary signaling to multilevel signaling by changing the voltage parameter, using multiple voltage levels (e.g., 4-level or 8-level PAM) to encode multiple bits per symbol, thereby increasing transmission speed while managing signal distortion through careful parameter optimization
2Reliability
If an interposer is used to maintain signal integrity, then signal quality is improved, but manufacturing cost increases
Solution Approach 1:
The patent explores alternative approaches that replace the expensive silicon interposer with cost-effective packaging substrate solutions, using standard PCB materials and processes to achieve acceptable signal integrity without the high cost of custom silicon interposers
3Speed
If the distance between logic chip and HBM is reduced, then transmission speed is improved, but signal distortion increases due to package substrate channels
Solution Approach 1:
The packaging substrate is designed with localized high-density wiring structures and controlled impedance traces specifically in the HBM-to-logic chip signal paths, providing optimal signal quality in critical areas while maintaining cost-effective overall packaging
Data Source
AI summary
A high bandwidth memory system includes a motherboard; and a semiconductor package coupled to the motherboard. The semiconductor package includes a package substrate mounted on the motherboard and including signal lines providing a plurality of channels; a first semiconductor device mounted on the package substrate and including a first physical layer (PHY) circuit; and a second semiconductor device mounted on the package substrate and including a second PHY circuit. The first semiconductor device and the second semiconductor device exchange a data signal with each other through the plurality of channels, the data signal is a multilevel signal having M levels, where M is a natural number greater than 2, and the first PHY circuit compensates for distortion of the channels and performs digital signal processing to compensate for a mismatch between the channels.