Multilevel Package Substrate Layout for ILD Crack Mitigation
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Solution Overview
Problem
Interfacial delamination and cracking in the interlayer or interlevel dielectric (ILD) material of semiconductor die metallization structures in multilevel package substrates lead to performance degradation and potential device failure, especially during temperature cycling, due to poor fracture strength and brittle mechanical behavior, which existing solutions attempt to address through increasing die top metal layer thickness or redesigning materials, but these approaches are costly and time-consuming.
Innovation Solution
A multilevel package substrate design where the second level has no conductive features under the peripheral contact portions of the first conductive features, reducing peeling stress and mitigating ILD cracking without additional cost or impact on electrical performance, by removing select amounts of metal directly under the conductive peripheral terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the die top metal layer thickness is increased to reduce peeling stress and prevent ILD cracking, then the mechanical strength and reliability are improved, but the device height increases and electrical circuit performance deteriorates
Solution Approach 1:
The patent removes the second level conductive features from areas directly under the peripheral contact portions of the first conductive features. This extraction of metal material eliminates the source of peeling stress that causes ILD cracking, while avoiding the need to increase the overall device height through thicker metal layers elsewhere in the structure.
Solution Approach 2:
The patent applies different structural configurations to different regions of the package substrate. The peripheral regions under contact portions have reduced metal density (no second level features), while other regions maintain full multilevel conductive structures. This localized modification addresses cracking susceptibility specifically where it occurs without compromising overall electrical performance or increasing device height globally.
2Reliability
If the die top metal layer thickness is increased to prevent ILD cracking, then the mechanical strength is improved, but the manufacturing cost increases
Solution Approach 1:
The patent removes unnecessary metal material from specific regions rather than adding material throughout the structure. This extraction approach reduces material consumption and simplifies the manufacturing process by eliminating the need for additional thick metal layer deposition, thereby reducing manufacturing costs while maintaining reliability.
3Reliability
If the die top metal layer thickness is increased to reduce peeling stress, then the interfacial adhesion is improved, but the device development time increases due to redesign requirements
Solution Approach 1:
The patent improves interfacial adhesion by removing the second level conductive features that generate peeling stress, rather than requiring a complete redesign of the metallization structure or terminal layout. This approach maintains compatibility with existing design rules and manufacturing processes, significantly reducing development time compared to comprehensive redesign approaches.
4Reliability
If second level conductive features are removed under peripheral contact portions, then peeling stress is reduced and ILD cracking is mitigated, but the structural complexity of the multilevel package substrate increases
Solution Approach 1:
The patent creates a non-uniform structure where the second level conductive features are selectively removed only in peripheral regions under contact portions, while being retained in interior regions. This localized differentiation addresses the specific cracking susceptibility at peripheral contacts without requiring complete structural redesign, balancing reliability improvement with manageable complexity.
Data Source
AI summary
An electronic device includes a multilevel package substrate and a semiconductor die, where the multilevel package substrate has first and second levels in respective first and second planes in a stack, the first level including a first conductive feature, and the second level including a second conductive feature, and the semiconductor die has a conductive peripheral terminal, a conductive interior terminal, a peripheral region, and an interior region. The peripheral region laterally surrounds the interior region and extends laterally between the interior region and the lateral sides of the semiconductor die, the conductive peripheral terminal extends from the peripheral region to the first level, the conductive interior terminal extends from the interior region to the first level, the peripheral terminal is coupled to a peripheral contact portion of the first conductive feature, and the second level has no conductive feature under the peripheral contact portion.