Multi-Level Semiconductor Test Structure for Fault Isolation

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Solution Overview

Problem

There is a continued desire for further scaling and reducing the size of field-effect transistors (FETs) beyond current techniques such as fin-shaped channels and stacked nanosheet channels, particularly for next-generation stacked FET devices.

Innovation Solution

The development of semiconductor test structures with multi-level wiring connections through contact structures, including vias and serial connections between frontside and backside wiring levels, allowing for advanced testing and isolation of devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multi-level wiring connections with contact structures are implemented, then testing capability and device isolation are improved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:

Improvetesting capabilityVSAvoidstructure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The test structure is divided into multiple discrete wiring levels (first side wiring levels and second side wiring levels) separated by a device layer. Contact structures (vias) segment the connection path into distinct layers, allowing independent testing of different device aspects while maintaining organizational clarity despite the multi-level complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar wiring to three-dimensional multi-level wiring by adding vertical contact structures (via) that penetrate the device layer. This vertical dimension enables connections between first side wiring levels and second side wiring levels, dramatically increasing testing capability while managing complexity through structured layering.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If multi-level wiring connections with contact structures are implemented, then testing capability and device isolation are improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improvetesting capabilityVSAvoidalignment precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The manufacturing process is segmented into distinct stages: forming first side wiring levels, creating contact structures through the device layer, and forming second side wiring levels. Each stage has specific precision requirements that are managed independently, allowing optimization of each manufacturing step rather than requiring all precision simultaneously.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Contact structures (via) are formed preliminarily to establish vertical pathways through the device layer before final wiring connections are made. This preliminary action defines the precise locations where connections will occur, guiding subsequent wiring formation and ensuring alignment precision is achieved at the critical via locations first.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250309055A1Testing structures for multi-level testing of semiconductor devices

Publication Date: 2025.10.02 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A semiconductor test structure comprises a first side, a second side located opposite the first side, and a device layer disposed between the first side and the second side. The device layer comprises a plurality of devices. At least one first side wiring level is disposed on the first side, and at least one second side wiring level is disposed on the second side. Two or more of the plurality of devices are electrically connected to each other through at least one contact structure connecting the at least one first side wiring level and the at least one second side wiring level.